An all-digital UWB TX is presented that generates PPM pulses with a center frequency
tunable to 3 channels in the 3.1-to-5GHz band without the use of an RF oscillator. A delay …

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in
phase-locked systems. In this digital calibration technique, there is no extra replica CP …

With the latest improvements in device size, power consumption, and communications,
sensor networks are becoming increasingly more popular. There has also been a great …

Ultra-wide-band (UWB) communication has a variety of applications ranging from wireless
USB to radio frequency (RF) identification tags. For many of these applications, energy is …

Electronic circuits operated in radiation environment such as space are adversely affected
by the ionizing radiation. The effects include generating a transient current, altering …

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based
clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to …

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been
developed in a 0.35-muhboxm CMOS technology. The proposed clock generator can …

A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm
CMOS technology is presented in this paper. The proposed ADDLL uses the modified …

This brief proposes a novel circuit architecture of an 11-bit reversible successive
approximation register (RSAR)-controlled all-digital delay-locked loop (DLL), which could …

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock
generator in low-power systems. The proposed DLL has a faster lock speed with the same …