Clock gating based energy efficient ALU design and implementation on FPGA
In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and
dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and …
dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and …
Energy efficient design and implementation of ALU on 40nm FPGA
B Pandey, J Yadav, YK Singh… - … Conference on Energy …, 2013 - ieeexplore.ieee.org
There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm
Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power …
Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power …
[PDF][PDF] Clock gating aware low power ALU design and implementation on FPGA
This paper deals with the design and implementation of a Clock Gating Aware Low Power
Arithmetic and Logic Unit that has been developed as part of low power processor design in …
Arithmetic and Logic Unit that has been developed as part of low power processor design in …
LVCMOS I/O standard based million MHz high performance energy efficient design on FPGA
In design and implementation of energy efficient counter for energy efficient processor, we
are using LVCMOS I/O standard in FPGA. CMOS technology is used to achieve energy …
are using LVCMOS I/O standard in FPGA. CMOS technology is used to achieve energy …
Low power VLSI circuit design with efficient HDL coding
In this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is
designed in **linx ISE 14.2 and implemented on high performance Virtex-6 FPGA …
designed in **linx ISE 14.2 and implemented on high performance Virtex-6 FPGA …
[PDF][PDF] Drive strength and LVCMOS based dynamic power reduction of ALU on FPGA
B Pandey, M Kumar, N Robert… - Lecture Notes on …, 2013 - academia.edu
In this paper, we achieve 35.9% dynamic power reduction and 36.11% dynamic current
reduction by shfting drive strength from 24mA to 2mA on LVCMOS25 when 2.5 V is output …
reduction by shfting drive strength from 24mA to 2mA on LVCMOS25 when 2.5 V is output …
Analysis of low power consumption techniques on FPGA for wireless devices
In present scenario, the portable wireless devices like mobile phones are used by almost
every human being for communication purpose. Mobile devices are equipped with a …
every human being for communication purpose. Mobile devices are equipped with a …
Thermal aware energy efficient bengali unicode reader in text analysis
In Text analysis, the current focus of researcher is on performance. There is a wide research
gap to design energy efficient hardware which is in use in text analysis. When room …
gap to design energy efficient hardware which is in use in text analysis. When room …
Output load capacitance based low power implementation of UART on FPGA
Core dynamic power is independent of output load capacitance. IO power and static power
is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs …
is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs …
Design and analysis of ALU for low power IOT centric processor architectures
G Verma - 2020 Global Conference on Wireless and Optical …, 2020 - ieeexplore.ieee.org
This research work proposed a low powered design of arithmetic and logical unit for IOT
centric processor architectures. As ALU is the main computation contraption in almost all the …
centric processor architectures. As ALU is the main computation contraption in almost all the …