Power dissipation accounts for high-performance digital systems in the deep sub-micron
region. As a result, power within compact systems is vital. This paper investigates four …

Recently power has become the most important factor in VLSI design. As clock network is
the largest design element in terms of power consumption in modern low-power Very Large …

Latch clustering is a critical stage to reduce power consumption at cost of timing disruption
during a modern SoC design flow. However, most existing latch clustering researches …

Flip-flops are simultaneously endpoints of combinational logic timing paths and leaf nodes
of clock networks. Hence, flip-flop placement significantly affects both circuit timing and clock …

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing
the power consumption and chip area of integrated circuits (ICs) during the physical …

Power dissipation accounts for high-performance digital systems in the deep sub-micron
region. As a result, power within compact systems is vital. This paper investigates four …