Interpolation is used to approximate the timing parameters of logic cells not specified in
timing tables. Bilinear interpolation has been taken for granted in the industry, but the error …

We propose a new modeling methodology using deep learning techniques for generating
timing models for Static Timing Analysis (STA). Current device behavior is non-linear, non …

Statistical timing characterization for modeling On-Chip Variation (OCV) is critical in current
technology nodes to avoid over-design and to improve design convergence and …

This paper presents a technique for the modeling and design of a nano scale CMOS inverter
circuit using artificial neural network and particle swarm optimization algorithm such that the …

This paper presents a fast method for timing characterization of standard cell library. It is
based on curve fitting to solve the CPU resources and storage issues for the generation of a …

We propose a modeling methodology for both leakage power consumption and delay of
basic CMOS digital gates in the presence of threshold voltage and mobility variations. The …

This article proposes a method for performing device-level variability-aware static timing
analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash …

标准单元库是芯片设计, 分析和验证的基础, 其生成需要耗费大量时间和服务器资源,
因此供应商往往只提供少量端角的标准单元库. 但是, 芯片性能, 功耗, 可靠性等指标的设计需要 …

Static timing analysis (STA), which is a part of design automation requires the generation
and storage of delay values for combinational standard cells and the setup and hold time …

Accurate estimation of delay is a major challenge in current nanometer regime using Non
Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear …