System, method, and computer program product for improving memory systems
MS Smith - US Patent 9,432,298, 2016 - Google Patents
H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …
state devices; Multistep manufacturing processes thereof the devices being of types …
Evaluating STT-RAM as an energy-efficient main memory alternative
In this paper, we explore the possibility of using STT-RAM technology to completely replace
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
DRAM in main memory. Our goal is to make STT-RAM performance comparable to DRAM …
EnerJ: Approximate data types for safe and general low-power computation
Energy is increasingly a first-order concern in computer systems. Exploiting energy-accuracy
trade-offs is an attractive choice in applications that can tolerate inaccuracies. Recent work …
trade-offs is an attractive choice in applications that can tolerate inaccuracies. Recent work …
RAIDR: Retention-aware intelligent DRAM refresh
Dynamic random-access memory (DRAM) is the building block of modern main memory
systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh …
systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh …
Flikker: Saving DRAM refresh-power through critical data partitioning
S Liu, K Pattabiraman, T Moscibroda… - Proceedings of the …, 2011 - dl.acm.org
Energy has become a first-class design constraint in computer systems. Memory is a
significant contributor to total system power. This paper introduces Flikker, an application …
significant contributor to total system power. This paper introduces Flikker, an application …
3D-stacked memory architectures for multi-core processors
GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …
thereby significantly reducing wire delay between the two. Previous studies have examined …
Self-optimizing memory controllers: A reinforcement learning approach
Efficiently utilizing off-chip DRAM bandwidth is a critical issuein designing cost-effective,
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …
Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design
This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior
research, including the recent work from Loh and Hill, have organized DRAM caches similar …
research, including the recent work from Loh and Hill, have organized DRAM caches similar …
A survey of architectural techniques for DRAM power management
S Mittal - … Journal of High Performance Systems Architecture, 2012 - inderscienceonline.com
Recent trends of CMOS technology scaling and wide-spread use of multicore processors
have dramatically increased the power consumption of main memory. It has been estimated …
have dramatically increased the power consumption of main memory. It has been estimated …
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic random access memory (MRAM) is a promising memory technology, which has
fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it …
fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it …