A hardware Trojan detection method for IoT sensors using side-channel activity magnifier
E Jedari, R Rashidzadeh - IEEE Internet of Things Journal, 2021 - ieeexplore.ieee.org
As the Internet of Things (IoT) technology matures and becomes widely adopted, security for
IoT networks remains the main concern for users and organizations across the globe. The …
IoT networks remains the main concern for users and organizations across the globe. The …
A Low Leakage Autonomous Data Retention Flip‐Flop with Power Gating Technique
X Fan, Y Wu, H Dong, J Hu - journal of electrical and computer …, 2014 - Wiley Online Library
With the scaling of technology process, leakage power becomes an increasing portion of
total power. Power gating technology is an effective method to suppress the leakage power …
total power. Power gating technology is an effective method to suppress the leakage power …
Promoting reflective thinking in teacher candidates: are digital video/multimedia portfolios a useful tool?
S Spurgeon, JL Bowen - International Conference on …, 2002 - ieeexplore.ieee.org
This research examined the effects of a process of digital video editing used to create a
multimedia portfolio on the quality of teacher candidates' critical reflections. Subjects were …
multimedia portfolio on the quality of teacher candidates' critical reflections. Subjects were …
Active-mode leakage power optimization using state-preserving techniques
AV Korshunov, PS Volobuev - … of IEEE East-West Design & Test …, 2014 - ieeexplore.ieee.org
As technology sizes shrink, the developers come upon a problem of leakage currents.
Among the different power reduction approaches there are power gating and clock gating …
Among the different power reduction approaches there are power gating and clock gating …
Hybrid approach of within-clock power gating and normal power gating to reduce power
Power gating (PG) is used to reduce leakage power by shutting down the power supply of
the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce …
the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce …
[PDF][PDF] Low power register design with integration clock gating and power gating
D Koteswara Rao, TR Pale, T Tools - International Journal of …, 2014 - academia.edu
In Integrated circuits a gargantuan portion of chip power is expended by clocking system
which comprises of timing elements such as flip-flops, latches and clock distribution network …
which comprises of timing elements such as flip-flops, latches and clock distribution network …
[PDF][PDF] DESIGN OF 7T SRAM FOR SECURITY ORIENTED APPLICATIONS
H Busigampala, B Pranathi, M Shivani, R Shivani - junikhyatjournal.org
Memory is a crucial component of any modern integrated device because of the ubiquity of
digital data. Additionally, it contributes significantly to the overall circuit power. The …
digital data. Additionally, it contributes significantly to the overall circuit power. The …
[PDF][PDF] Clock gating and run time power gating integration by using dual stacking technique
BB Dedeepya, GAES Kumar - international journal of research studies in …, 2014 - ijrsset.org
This Paper describes the facility Gating duration system that contains of temporal
arrangement components like flip flops, latches and clock distribution network. This paper …
arrangement components like flip flops, latches and clock distribution network. This paper …
Self-Power Saving Technique in State Machine Circuit of Automatic Teller Machine Application
MH Vo - Journal of Low Power Electronics, 2019 - ingentaconnect.com
In a finite state machine (FSM), there is only one active state while the other states are in idle
states simultaneously. Thus, only one state is required to power up, the other states can be …
states simultaneously. Thus, only one state is required to power up, the other states can be …
[CITA][C] Develo** a 7-transistor SRAM for use in security-critical contexts
D Venu, TM Kumar, R Haritha