The classical occupancy problem is concerned with studying the number of empty bins
resulting from a random allocation of m balls to n bins. We provide a series of tail bounds on …

The design of portable battery operated multimedia devices requires energy-efficient
multiplication circuits. This paper presents a novel approach to reduce power consumption …

Reducing the power dissipation of parallel multipliers is important in the design of digital
signal processing systems. In many of these systems, the products of parallel multipliers are …

Truncated multiplication can be used to significantly reduce the power dissipation for
applications that do not require correctly-rounded results. This paper presents an efficient …

Approaches for maximizing throughput of self-timed multiply–accumulate units (MACs) are
developed and assessed using the NULL convention logic paradigm. In this class of self …

We describe a micropower 16/spl times/16-bit multiplier (18.8/spl mu/W/MHz@ 1.1 V) for low-
voltage power-critical low speed (/spl les/5 MHz) applications including hearing aids. We …

Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-
rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is …

Abstract NULL Convention Logic (NCL) provides an asynchronous design methodology
employing dual-rail signals, quad-rail signals, or other Mutually Exclusive Assertion Groups …

Before signals of a digital circuit reach steady state, gates can have multiple transitions.
Since the power is dissipated in a CMOS circuit mainly due to transitions, the extra …

Various 16-bit multiplier architectures are compared in terms of dissipated energy,
propagation delay, energy-delay product (EDP), and area occupation, in view of low-power …