Performance analysis: D-Latch modules designed using 18nm FinFET Technology

RR Vallabhuni, G Yamini, T Vinitha… - … Conference on Smart …, 2020 - ieeexplore.ieee.org
In general, a latch also known as level triggered device is used to store single bit
information. Also, the latch is considered as a building block for sequential circuits. The …

Compensation and calibration techniques for current-steering DACs

SM McDonnell, VJ Patel, L Duncan… - IEEE Circuits and …, 2017 - ieeexplore.ieee.org
Digital-to-analog converters (DACs) are pervasive, critical components for radios and
various signal processing systems. Therefore, a myriad of research efforts, covering …

A 4× 6.25-Gbps Serial Link Transmitter Core in 0.18-μm CMOS for High-Speed Front-End ASICs

J Guo, J Qin, J Li, X Bin, X Yang, H **e… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
High-speed serial link transmitters have been widely integrated in front-end ASICs.
However, it's difficult to achieve high data bandwidth, low power consumption and low jitter …

An improved high speed, and low voltage CMOS current mode logic latch

O Lozada, G Espinosa - Analog Integrated Circuits and Signal Processing, 2017 - Springer
A high-speed, low voltage CMOS current mode logic (CML) latch, that has high input, and
output voltage dynamic ranges, is proposed in this paper. The input common-mode voltage …

Design concepts of low-noise amplifier for radio frequency receivers

S Manickam - RF Systems, Circuits and Components, 2018 - books.google.com
The development of high-performance radio frequency (RF) transceivers or multistandard/
reconfigurable receivers requires an innovative RF front-end design to ensure the best from …

MOS current mode logic realization of digital arithmetic circuits

YM El-Hariry, AH Madian - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
In this paper, MOS current mode logic (MCML) and dynamic current mode logic (DyCML)
techniques are analyzed and applied to the generation of digital arithmetic circuits. A full …

[PDF][PDF] Design of low voltage D-flip flop using MOS current mode logic (MCML) For high frequency applications with EDA tool

KK Mandrumaka, A Sajja… - International Journal of …, 2017 - academia.edu
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state
buffers. In Mos current mode logic (MCML) current section is improves the performance and …

Design and Implementation of Power Efficient 8: 1 Multiplexer using PTL Technology

S Agarwal, N Pathak… - 2023 2nd International …, 2023 - ieeexplore.ieee.org
The development in the methodologies of fundamental functional units of digital systems
have raised the attention due to advancement in CMOS technology. Continuous demand of …

[BOK][B] Compensation and Calibration Techniques for High Performance Current-Steering DACs

SM McDonnell - 2016 - search.proquest.com
A myriad of research efforts, covering architectural, circuit and technological aspects, have
been made towards improving the performance of digital-to-analog converters (DACs) …

[PDF][PDF] Ultrafast Spin Dynamics: The Effect of Colored Noise

U Atxitia, O Chubykalo-Fesenko, RW Chantrell… - scholar.archive.org
This chapter provides a practical strategy to realize accurate and robust control for 6 DOFs
(degrees of freedom) parallel robots. The presented approach consists in two parts. The first …