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A review of InP/InAlAs/InGaAs based transistors for high frequency applications
This paper presents an overview of the rapid progress being made in the development of
InP based devices for high speed applications. Over the past few decades, major aero …
InP based devices for high speed applications. Over the past few decades, major aero …
Ultimate scaling of CMOS logic devices with Ge and III–V materials
M Heyns, W Tsai - Mrs bulletin, 2009 - cambridge.org
Over the years, many new materials have been introduced in advanced complementary
metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the …
metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the …
Challenges of 22 nm and beyond CMOS technology
R Huang, HM Wu, JF Kang, DY **ao, XL Shi… - Science in China Series …, 2009 - Springer
It is predicted that CMOS technology will probably enter into 22 nm node around 2012.
Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and …
Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and …
InGaAs tunneling field-effect-transistors with atomic-layer-deposited gate oxides
In 0.7 Ga 0.3 As tunneling field-effect-transistors (TFETs) using the p+(6 nm)/undoped (6 nm)
tunneling junction with 5-nm HfO 2 gate oxides have been demonstrated with an on-current …
tunneling junction with 5-nm HfO 2 gate oxides have been demonstrated with an on-current …
First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching
The first well-behaved inversion-mode InGaAs FinFET with gate length down to 100 nm with
ALD Al 2 O 3 as gate dielectric has been demonstrated. Using a damage-free sidewall …
ALD Al 2 O 3 as gate dielectric has been demonstrated. Using a damage-free sidewall …
Scalability of sub-100 nm InAs HEMTs on InP substrate for future logic applications
We have experimentally studied the scaling behavior of sub-100-nm InAs high-electron
mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These …
mobility transistors (HEMTs) on InP substrate from the logic operation point of view. These …
Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth
We report Al 2 O 3 Zln 0.53 Ga 0.47 As MOSFETs having both self-aligned in situ Mo
source/drain ohmic contacts and self-aligned InAs source/drain n+ regions formed by MBE …
source/drain ohmic contacts and self-aligned InAs source/drain n+ regions formed by MBE …
N-FET with a highly doped source/drain and strain booster
JC Lin, CH Yu - US Patent 8,247,285, 2012 - Google Patents
US PATENT DOCUMENTS 6,271,551 B1 8, 2001 Schmitz et al. 6,605,498 B1 8/2003 Murthy
et al. 6,881,635 B1 4/2005 Chidambarrao et al. 6,977.400 B2 12/2005 Puchner et al …
et al. 6,881,635 B1 4/2005 Chidambarrao et al. 6,977.400 B2 12/2005 Puchner et al …
Impact of forming gas annealing on the performance of surface-channel In0. 53Ga0. 47As MOSFETs with an ALD Al2O3 gate dielectric
We investigated the effect of forming gas (5% H 2/95% N 2) annealing on surface-channel In
0.53 Ga 0.47 As MOSFETs with atomic-layer-deposited Al 2 O 3 as the gate dielectric. We …
0.53 Ga 0.47 As MOSFETs with atomic-layer-deposited Al 2 O 3 as the gate dielectric. We …
Effects of ZrO2/Al2O3 Gate-Stack on the Performance of Planar-Type InGaAs TFET
We investigate the impact of gate-stack engineering using W/ZrO 2/Al 2 O 3 on the
performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that …
performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that …