Instruction set simulators (ISSs) model the functional behavior of embedded processors for
early software development. While they offer high simulation speeds, an ISS usually does …

This thesis focuses on automatically synthesizing instruction set processors using High-
Level Synthesis (HLS). In particular, we aim at automatically generating in-order pipelined …

Recently proposed real-time memorycontrollers tackle the performance-predictability
tradeoffby trying to offer the best of both worlds. However, as a consequence, designs have …

The translation of binary code to higher-level models has wide applications, including
decompilation, binary analysis, and binary rewriting. This calls for high reliability of the …

응용 특화 프로세서들은 목표 도메인에서의 성능 극대화를 위해 자주 쓰이는 연산들을 위한
특화 명령어들을 가진다. 응용 특화 프로세서를 위한 프로그램은 특화 명령어를 사용하기 …

Complex hardware systems can be designed by breaking down their behaviour into high‐
level descriptions of constituent scenarios and then composing these scenarios into an …

In this thesis, I will explore different approaches to modelling the Gen-Z specifications [60].
The Gen-Z interconnect enables new system topologies, such as memory-centric systems …

The behaviour of many systems can be partitioned into scenarios. These facilitate engineers'
understanding of the specifications, and can be composed into efficient implementations via …