In this paper, a new domino circuit is proposed, which has a lower leakage and higher noise
immunity without dramatic speed degradation for wide fan-in gates. The technique which is …

With current tools and technology, someone who has physical access to a chip can extract
the detailed layout of the integrated circuit (IC). By using advanced visual imaging …

Dynamic logic circuits suffer from leakage current during their evaluation period causing
output voltage degradation. Although the keeper transistor is added to protect the output …

In this paper, a new leakage-tolerant domino circuit is presented which has lower power
consumption and higher noise immunity without significant delay increment for wide fan-in …

Noise immunity is an important concern in deep nano-scale technologies, especially for high
fan-in gates. In this paper, a new domino circuit technique is proposed by which the noise …

Low power, low cost, less chip area, and high speed have become the requirements in the
present generation of electronic circuits in nano-sacle technology. Due to the requirement of …

Clock Controlled Dual keeper Domino logic structures (CCDD _1 and CCDD _2) for
achieving a high‐speed performance with low power consumption and a good noise margin …

In this work, a new technique for domino circuit is proposed to reduce the process variations
and power dissipation with optimized delay for wide fan-in OR logic. Two methods are used …

Domino circuit topology for high-speed operation, robustness and lower power consumption
is quintessential in design of digital systems. In this paper, various high speed and robust …

This paper proposes a novel method to control leakage and noise in domino circuits for wide
fan-in OR logic with low power consumption, low process variation, and higher noise margin …