In accordance with the described techniques for bank-level parallelism for processing in
memory, a plurality of commands are received for execution by a processing in memory …

BACKGROUND [0002] Memory devices are typically provided as internal, semiconductor,
integrated circuits in computers or other electronic systems. There are many different types …

An apparatus includes a memory controller that includes logic to receive a first memory
request having a first request type and a second memory request having a second request …

Adaptive scheduling of memory requests and processing-in-memory requests is described.
In accordance with the described techniques, a memory controller receives a plurality of …

A method, a unit and circuits for implementing Boolean logics based on computing-in-
memory transistors. The method is implemented by using the characteristics and the read …

US11630605B1 - Methods and systems for processing read-modify-write requests - Google
Patents US11630605B1 - Methods and systems for processing read-modify-write requests …

Scheduling requests of multiple processing-in-memory threads and requests of multiple non-
processing-in-memory threads is described. In accordance with the described techniques, a …

Disclosed is a memory device including a plurality of memory banks, each of which performs
an operation based on first operand data including pieces of first unit data and second …

2022-07-14 Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC reassignment
MICROSOFT TECHNOLOGY LICENSING, LLC ASSIGNMENT OF ASSIGNORS INTEREST …

US11262949B2 - Command throughput in PIM-enabled memory using available data bus
bandwidth - Google Patents US11262949B2 - Command throughput in PIM-enabled memory …