RISC-H: Rowhammer Attacks on RISC-V

M Marazzi, K Razavi - 4th Workshop on DRAM Security …, 2024 - research-collection.ethz.ch
The first high-end RISC-V CPU with DDR4 support has been released just a few months
ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear …

Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance

A Olgun, F Bostanci, IE Yuksel, O Canpolat… - arxiv preprint arxiv …, 2025 - arxiv.org
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read
disturbance mitigations rely on accurate and exhaustive characterization of the read …

REFault: A Fault Injection Platform for Rowhammer Research on DDR5 Memory

S Gloor, P Jattke, K Razavi - Proceedings of the Microarchitecture …, 2025 - tosc.iacr.org
DDR5 is showing increased resistance to Rowhammer attacks compared to previous
generations. The minimum hammer count (HCmin) is a metric to assess the susceptibility of …