A survey of computer architecture simulation techniques and tools

A Akram, L Sawalha - Ieee Access, 2019 - ieeexplore.ieee.org
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …

The gem5 simulator: Version 20.0+

J Lowe-Power, AM Ahmad, A Akram, M Alian… - arxiv preprint arxiv …, 2020 - arxiv.org
The open-source and community-supported gem5 simulator is one of the most popular tools
for computer architecture research. This simulation infrastructure allows researchers to …

The gem5 simulator

N Binkert, B Beckmann, G Black, SK Reinhardt… - ACM SIGARCH …, 2011 - dl.acm.org
The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS
[9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and …

A detailed and flexible cycle-accurate network-on-chip simulator

N Jiang, DU Becker, G Michelogiannakis… - … analysis of systems …, 2013 - ieeexplore.ieee.org
Network-on-Chips (NoCs) are becoming integral parts of modern microprocessors as the
number of cores and modules integrated on a single chip continues to increase. Research …

DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling

C Sun, CHO Chen, G Kurian, L Wei… - 2012 IEEE/ACM …, 2012 - ieeexplore.ieee.org
With the rise of many-core chips that require substantial bandwidth from the network on chip
(NoC), integrated photonic links have been investigated as a promising alternative to …

Syncron: Efficient synchronization support for near-data-processing architectures

C Giannoula, N Vijaykumar… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Near-Data-Processing (NDP) architectures present a promising way to alleviate data
movement costs and can provide significant performance and energy benefits to parallel …

Modular routing design for chiplet-based systems

J Yin, Z Lin, O Kayiran, M Poremba… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking
of an SoC into smaller" chiplets." A chiplet-based SoC design process has the promise to …

Orion 2.0: A power-area simulator for interconnection networks

AB Kahng, B Li, LS Peh… - IEEE Transactions on Very …, 2011 - ieeexplore.ieee.org
As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the
scalable fabric for interconnecting the cores. With power now the first-order design …

Review of 3D networks-on-chip simulators and plugins

AAJ Al-Hchaimi, WN Flayyih, F Hashim… - 2021 IEEE Asia …, 2021 - ieeexplore.ieee.org
A comprehensive review focuses on 3D network-on-chip (NoC) simulators and plugins while
paying attention to the 2D simulators as the baseline is presented. Discussions include the …

Splash-3: A properly synchronized benchmark suite for contemporary research

C Sakalis, C Leonardsson, S Kaxiras… - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
Benchmarks are indispensable in evaluating the performance implications of new research
ideas. However, their usefulness is compromised if they do not work correctly on a system …