Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

The Nesterov's method approach to analytic placement has recently demonstrated strong
solution quality and scalability. We dissect the previous implementation strategy and show …

At modern technology nodes, improving routability and reducing total wirelength are no
longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve …

Protecting intellectual property (IP) in electronic circuits has become a serious challenge in
recent years. Logic locking/encryption and layout camouflaging are two prominent …

Placement is central to IC physical design: it determines spatial embedding, and hence
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …

In this work, we advance the security promise of split manufacturing through judicious
handling of interconnects. First, we study the cost-security tradeoffs underlying for split …

Split manufacturing (SM) seeks to protect against piracy of intellectual property (IP) in chip
designs. Here we propose a scheme to manipulate both placement and routing in an …

This paper describes the latest release of the DATC Robust Design Flow (RDF), RDF-2021,
which has several key additions to expand its horizons. The Chisel/FIRRTL compiler is now …

Protecting intellectual property (IP) has become a serious challenge for chip designers. Most
countermeasures are tailored for CMOS integration and tend to incur excessive overheads …

Editor's notes: In this article, the authors introduce RosettaStone, an open and extensible
foundation, which leverages a standard physical design data model (LEF/DEF 5.8) and …