[HTML][HTML] Reliability-aware resource management in multi-/many-core systems: A perspective paper

SS Sahoo, B Ranjbar, A Kumar - Journal of Low Power Electronics and …, 2021 - mdpi.com
With the advancement of technology scaling, multi/many-core platforms are getting more
attention in embedded systems due to the ever-increasing performance requirements and …

Cross-layer fault-tolerant design of real-time systems

SS Sahoo, B Veeravalli, A Kumar - 2016 IEEE International …, 2016 - ieeexplore.ieee.org
Continued transistor scaling and increasing power density has resulted in considerable
increase in fault rates of nano-technology systems. Cross-layer fault tolerance techniques …

CL (R) early: An early-stage DSE methodology for cross-layer reliability-aware heterogeneous embedded systems

SS Sahoo, B Veeravalli, A Kumar - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
Cross-layer reliability (CLR) presents a cost-effective alternative to traditional single-layer
design in resource-constrained embedded systems. CLR provides the scope for leveraging …

A hybrid agent-based design methodology for dynamic cross-layer reliability in heterogeneous embedded systems

SS Sahoo, B Veeravalli, A Kumar - Proceedings of the 56th Annual …, 2019 - dl.acm.org
Technology scaling and architectural innovations have led to increasing ubiquity of
embedded systems across applications with widely varying and often constantly changing …

Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives

SS Sahoo, A Kumar, M Decky, SCB Wong… - Proceedings of the …, 2021 - dl.acm.org
Modern embedded systems need to cater for several needs depending upon the application
domain in which they are deployed. For example, mixed-critically needs to be considered for …

CLRFrame: An analysis framework for designing cross-layer reliability in embedded systems

SS Sahoo, B Veeravalli, A Kumar - 2018 31st International …, 2018 - ieeexplore.ieee.org
Continued transistor scaling and increasing power density have led to considerable
increase in fault rates in silicon nanotechnology-based real-time systems. Instead of fixing …

Using Monte Carlo tree search for EDA–A case-study with designing cross-layer reliability for heterogeneous embedded systems

SS Sahoo, A Kumar - … on Very Large Scale Integration (VLSI …, 2021 - ieeexplore.ieee.org
Continued transistor scaling and increasing power density have led to considerable
increase in fault-rates in silicon nanotechnology-based real-time systems. Cross-layer fault …

QoS-aware cross-layer reliability-integrated FPGA-based dynamic partially reconfigurable system partitioning

SS Sahoo, TDA Nguyen, B Veeravalli… - … Conference on Field …, 2018 - ieeexplore.ieee.org
Dynamic Partial Reconfiguration (DPR) can be used for time-sharing of computing
resources within Partially Reconfigurable Regions (PRRs) in FPGA-based systems. The …

[PDF][PDF] Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper. J. Low Power Electron. Appl. 2021, 11, 7

SS Sahoo, B Ranjbar, A Kumar - 2021 - cfaed.tu-dresden.de
With the advancement of technology scaling, multi/many-core platforms are getting more
attention in embedded systems due to the ever-increasing performance requirements and …

Fault Tolerant Architectures

SS Sahoo, A Das, A Kumar - Handbook of Computer Architecture, 2023 - Springer
Fault-tolerant computing has been the cornerstone of reliable computing using electronic
systems. Traditionally, fault-tolerant system design has been primarily driven by the system's …