SRAM stability analysis and performance–reliability tradeoff for different cache configurations
Bias temperature instability (BTI), hot carrier injection (HCI), gate-oxide time-dependent
dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of …
dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of …
Memory and logic lifetime simulation systems and methods
Aspects of the disclosed technology include a method including extracting, by a processor, a
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …
plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the …
Performance Degradation Analysis and Hot-Carrier Injection Impact on the Lifetime Prediction of Voltage Control Oscillator
This paper analyzes the root cause of performance degradation and the impact of hot-carrier
injection (HCI) on the lifetime prediction of an LC voltage-controlled oscillator (LC-VCO) …
injection (HCI) on the lifetime prediction of an LC voltage-controlled oscillator (LC-VCO) …
Reliability analysis of spintronic device based logic and memory circuits
Y Wang - 2017 - pastel.hal.science
Spin transfer torque magnetic tunnel junction (STT-MTJ) has been considered as a
promising candidate for next generation of non-volatile memories and logic circuits, because …
promising candidate for next generation of non-volatile memories and logic circuits, because …
Processor-level reliability simulator for time-dependent gate dielectric breakdown
Time-dependent gate dielectric breakdown (TDDB) is a leading reliability concern for
modern microprocessors. In this paper, a framework is proposed to analyze the impact of …
modern microprocessors. In this paper, a framework is proposed to analyze the impact of …
A physics-based statistical model for reliability of STT-MRAM considering oxide variability
A physics-based statistical model considering oxide thickness (T ox) variability is proposed
for evaluating the impact of time-dependent dielectric breakdown (TDDB) on the …
for evaluating the impact of time-dependent dielectric breakdown (TDDB) on the …
Negative bias temperature instability and gate oxide breakdown modeling in circuits with die-to-die calibration through power supply and ground signal …
With the scaling of CMOS technology, negative bias temperature instability (NBTI) and gate
oxide breakdown (GOBD) are serious issues for transistors. Normally, degradation due to …
oxide breakdown (GOBD) are serious issues for transistors. Normally, degradation due to …
Modeling for SRAM reliability degradation due to gate oxide breakdown with a compact current model
Gate oxide breakdown (GOBD) degrades the performance of SRAMs. In this paper, a
modeling methodology for SRAM reliability degradation due to GOBD is implemented with a …
modeling methodology for SRAM reliability degradation due to GOBD is implemented with a …
Statistical SBD modeling and characterization and its impact on SRAM cells
In this paper, we present a physics-based SPICE model for statistical soft breakdown (SBD)
in ultrathin oxide. Statistical SBD induces an increase in gate leakage current (IG_BD) …
in ultrathin oxide. Statistical SBD induces an increase in gate leakage current (IG_BD) …
Gate oxide breakdown parameter extraction with ground and power supply signature measurements
Gate oxide breakdown (GOBD) is a serious reliability issue for MOS transistors. Wearout due
to GOBD is traditionally modeled based on test structure data. In this paper, we present a …
to GOBD is traditionally modeled based on test structure data. In this paper, we present a …