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Hardware assisted remote transactional memory
M Ono - US Patent 10,963,383, 2021 - Google Patents
Hardware assisted remote transactional memory including receiving, from a first remote
processor over a high-speed communications fabric, an indication of a beginning of a first …
processor over a high-speed communications fabric, an indication of a beginning of a first …
Storage device with reduced communication overhead using hardware logic
W Choi, YW Kim, DE Shin, YC Jo - US Patent 11,435,947, 2022 - Google Patents
A storage device includes an input stage receiving a first command, a queue manager
allocating a first queue entry for the first command, a pre-processor storing the first command …
allocating a first queue entry for the first command, a pre-processor storing the first command …
Draining operation for draining dirty cache lines to persistent memory
An apparatus has processing circuitry with support for transactional memory, and a cache
hierarchy comprising at least two levels of cache. In response to a draining trigger event …
hierarchy comprising at least two levels of cache. In response to a draining trigger event …
Storage device with reduced communication overhead using hardware logic
W Choi, YW Kim, DE Shin, YC Jo - US Patent 12,019,918, 2024 - Google Patents
A storage device includes an input stage receiving a first command, a queue manager
allocating a first queue entry for the first command, a pre-processor storing the first command …
allocating a first queue entry for the first command, a pre-processor storing the first command …
Concurrency control method of database transaction combining optimistic lock and pessimistic lock
M Liu, C Guowu, HE Fangling - US Patent 11,263,197, 2022 - Google Patents
(57) ABSTRACT A concurrency control method of database transaction com bining an
optimistic lock and a pessimistic lock includes: integrating a lock in each fragment in a …
optimistic lock and a pessimistic lock includes: integrating a lock in each fragment in a …
Apparatus and data processing method for transactional memory
In an apparatus with transactional memory support circuitry, for a first type of transaction
started using a first type of transaction start instruction, commitment of results of instructions …
started using a first type of transaction start instruction, commitment of results of instructions …
Transaction nesting depth testing instruction
a data processing system may execute a number of threads of data processing. Sometimes,
the threads may need to access a shared resource and the nature of the data processing …
the threads may need to access a shared resource and the nature of the data processing …
Identifying read-set information based on an encoding of replaceable-information values
DGP Payet, L Garcia, N Bondarenko… - US Patent …, 2020 - Google Patents
An apparatus comprises processing circuitry, transactional memory support circuitry and a
cache. The processing circuitry processes threads of data processing, and the trans actional …
cache. The processing circuitry processes threads of data processing, and the trans actional …