A primer on design aspects and recent advances in shuffle exchange multistage interconnection networks
Interconnection networks provide an effective means by which components of a system such
as processors and memory modules communicate to provide reliable connectivity. This …
as processors and memory modules communicate to provide reliable connectivity. This …
Ready: A fine-grained multithreading overlay framework for modern cpu-fpga dataflow applications
In this work, we propose a framework called REconfigurable Accelerator DeploY (READY),
the first framework to support polynomial runtime map** of dataflow applications in high …
the first framework to support polynomial runtime map** of dataflow applications in high …
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
Coarse-grained reconfigurable architecture has emerged as a promising model for
embedded systems as a solution to reduce the complexity of FPGA synthesis and map** …
embedded systems as a solution to reduce the complexity of FPGA synthesis and map** …
You only traverse twice: A yott placement, routing, and timing approach for cgras
Coarse-grained reconfigurable architecture (CGRA) map** involves three main steps:
placement, routing, and timing. The map** is an NP-complete problem, and a common …
placement, routing, and timing. The map** is an NP-complete problem, and a common …
A vision system for monitoring intermodal freight trains
We describe the design and implementation of a vision based Intermodal Train Monitoring
System (ITMS) for extracting various features like length of gaps in an intermodal (IM) train …
System (ITMS) for extracting various features like length of gaps in an intermodal (IM) train …
Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime
Cloud FPGAs provide new energy‐efficient opportunities to design dataflow accelerators.
Nevertheless, FPGAs still have challenges to overcome for widespread usages, such as …
Nevertheless, FPGAs still have challenges to overcome for widespread usages, such as …
Plain: Ferramenta para Desenvolvimento de Aceleradores para Overlays em FPGA na Nuvem em Tempo de Execução
FPGAs provide an energy-efficient solution to design data-flow cloud accelerators.
Nevertheless, there are some challenges to widespread usage as the compiling time …
Nevertheless, there are some challenges to widespread usage as the compiling time …
Uma heurística polinomial para escalonamento de loops em arquiteturas reconfiguráveis de grão grosso
VD Lopes - 2013 - locus.ufv.br
Atualmente as arquiteturas reconfiguráveis são atrativas em desempenho e baixo consumo
de energia para aplicações com laços de computação intensiva. FPGAs são arquiteturas de …
de energia para aplicações com laços de computação intensiva. FPGAs são arquiteturas de …
[PDF][PDF] A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors
V Dumitriu - Ryerson University, Toronto, Canada, 2015 - rshare.library.torontomu.ca
ABSTRACT A number of modern digital processing systems implement complex multi-mode
applications with high performance requirements and strict operating constraints; examples …
applications with high performance requirements and strict operating constraints; examples …
Problem oriented approach to hardware-assisted algorithm design in c: A case study for scheduling, placement and routing
L Mucida, V Lopes, W Meireles… - 2012 13th Symposium …, 2012 - ieeexplore.ieee.org
This work presents a problem oriented approach to introduce the design of hardware
assisted algorithms. A scheduling, placement and routing problem for coarse-grained …
assisted algorithms. A scheduling, placement and routing problem for coarse-grained …