A DfT Strategy for Guaranteeing ReRAM's Quality after Manufacturing
Memristive devices have become promising candidates to complement the CMOS
technology, due to their CMOS manufacturing process compatibility, zero standby power …
technology, due to their CMOS manufacturing process compatibility, zero standby power …
Exploring an on-chip sensor to detect unique faults in RRAMs
Memristive devices have become promising candidates to complement and/or replace the
CMOS technology, due to their CMOS manufacturing process compatibility, zero standby …
CMOS technology, due to their CMOS manufacturing process compatibility, zero standby …
CD-DFT: A current-difference design-for-testability to detect short defects of STT-MRAM under process variations
This work presents an efficient test technique for detecting resistive short defects in STT-
MRAM arrays. The proposed technique is based on monitoring the current mismatch flowing …
MRAM arrays. The proposed technique is based on monitoring the current mismatch flowing …
A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs
Abstract Resistive defects in FinFET SRAMs are an important challenge for manufacturing
test in submicron technologies, as they may cause dynamic faults, which are hard to detect …
test in submicron technologies, as they may cause dynamic faults, which are hard to detect …
A DFT scheme to improve coverage of hard-to-detect faults in FinFET SRAMs
Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD)
faults always cause incorrect behavior, and therefore are easily detected by applying …
faults always cause incorrect behavior, and therefore are easily detected by applying …
LCHC-DFT: A low-cost high-coverage design-for-testability technique to detect hard-to-detect faults in STT-MRAMs in the presence of process variations
This paper proposes a low-cost yet high-coverage design-for-testability (DFT) scheme for
improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on …
improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on …
H2C-TM: A Hybrid High Coverage Test Method for Improving the Detection of HtD Faults in STT-MRAMs
This paper proposes a design-for-testability (DFT) scheme and a test method to improve the
detection of hard-to-detect (HtD) faults of STT-MRAMs. The proposed DFT scheme …
detection of hard-to-detect (HtD) faults of STT-MRAMs. The proposed DFT scheme …
Robust detection of bridge defects in STT-MRAM cells under process variations
AF Gomez, F Forero, K Roy… - 2018 IFIP/IEEE …, 2018 - ieeexplore.ieee.org
Spin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising memory technology due to
its ultra-integration density capability; nanosecond read and write operation speeds and …
its ultra-integration density capability; nanosecond read and write operation speeds and …
On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory
Rapid advancement in deep submicron technology has resulted in the highest occupancy of
memory on system-on-chip. The impact of process variations has increased with advanced …
memory on system-on-chip. The impact of process variations has increased with advanced …
An efficient wavelet based transient current test towards detection of data retention faults in SRAM
S NM - Journal of Electronic Testing, 2019 - Springer
Advancements in integrated circuit technologies, increasing manufacturing complexity and
incessant device scaling inflict new challenges in memory testing and demand for new …
incessant device scaling inflict new challenges in memory testing and demand for new …