In this article, we developed a massively parallel gate-level logical simulator to address the
ever-increasing computing demand for VLSI verification. To the best of the authors' …

A new fault simulator (VFSIM) for synchronous sequential circuits has been developed and
applied to random access scan circuits of several hundred LSIs in mainframe computers …

We present a new multiprocessor sequential circuit fault simulator, Zamlog, based on a
novel uniprocessor simulator, Zambezi. Both the fault and test sets are partitioned for …

Sequential circuit fault simulation is a compute-intensive problem. Parallel simulation is one
method to reduce fault simulation time. In this paper, we discuss a novel technique to …

Logic simulation has become the bottleneck of today's integrated circuit (IC) design projects.
For instance, over 80% of the IC design turn-around time of NVIDIA is spent on logic …

Due to the growth of design size and complexity, design verification is an important aspect of
the Logic Circuit development process. The purpose of verification is to validate that the …