Virtual Prototypes (VPs) have been now widely adopted by industry as platforms for early
SW development, HW/SW co-verification, performance analysis and architecture …

Traditional timing analysis, such as worst-case execution time analysis, is normally applied
only in the late stages of embedded system software development, when the hardware is …

With traditional cycle-accurate or instruction-set simulations of processors often being too
slow, host-compiled or source-level software execution approaches have recently become …

With ever increasing design complexities, traditional cycle-accurate or instruction-set
simulations are often too slow or too inaccurate for system prototy** in early design …

The validation of system models at the transaction-level typically relies on discrete event
(DE) simulation. In order to reduce simulation time, parallel discrete event simulation (PDES) …

Consideration of an embedded system's timing behaviour and power consumption at system-
level is an ambitious task. Sophisticated tools and techniques exist for power and timing …

With increasing complexity of today's embedded systems, research has focused on
develo** fast, yet accurate high-level and executable models of complete platforms …

Source code instrumentation is a widely used method to generate fast software simulation
models by annotating timing information into application source code. Source-level …

This paper presents a hybrid cache analysis for the simulation-based evaluation of data
caches in embedded systems. The proposed technique uses static analyses at the machine …

Recently, source-level software models are increasingly used for software simulation in TLM
(Transaction Level Modeling)-based virtual prototypes of multicore systems. A source-level …