Progress and challenges in VLSI placement research
Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …
performed over the last 50 years addressed numerous aspects of global and detailed …
ISPD 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement
The ISPD~ 2015 placement-contest benchmarks include all the detailed pin, cell, and wire
geometry constraints from the 2014 release, plus (a) added fence regions and placement …
geometry constraints from the 2014 release, plus (a) added fence regions and placement …
NTUplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints
CC Huang, HY Lee, BQ Lin, SW Yang… - … on Computer-Aided …, 2017 - ieeexplore.ieee.org
A placer without considering modern technology and region constraints could generate
solutions with irresolvable detailed-routing (DR) violations or even illegal solutions. This …
solutions with irresolvable detailed-routing (DR) violations or even illegal solutions. This …
Mixed-cell-height legalization considering technology and region constraints
Mixed-cell-height circuits have become popular in advanced technologies for better power,
area, routability, and performance tradeoffs. With technology and region constraints imposed …
area, routability, and performance tradeoffs. With technology and region constraints imposed …
Eh? Placer: A high-performance modern technology-driven placer
The placement problem has become more complex and challenging due to a wide variety of
complicated constraints imposed by modern process technologies. Some of the most …
complicated constraints imposed by modern process technologies. Some of the most …
Explainable DRC hotspot prediction with random forest and SHAP tree explainer
With advanced technology nodes, resolving design rule check (DRC) violations has become
a cumbersome task, which makes it desirable to make predictions at earlier stages of the …
a cumbersome task, which makes it desirable to make predictions at earlier stages of the …
Grid-based framework for routability analysis and diagnosis with conditional design rules
Pin accessibility encounters nontrivial challenges due to the smaller number of routing
tracks, higher pin density, and more complex design rules. Consequently, securing design …
tracks, higher pin density, and more complex design rules. Consequently, securing design …
Fast and precise routability analysis with conditional design rules
As pin accessibility encounters more challenges due to the less number of tracks, higher pin
density, and more complex design rules, routability has become one bottleneck of sub-10 …
density, and more complex design rules, routability has become one bottleneck of sub-10 …
Integrating operations research into very large-scale integrated circuits placement design: A review
The placement stage of the physical design of very large-scale integrated circuits (VLSI)
specifies the arrangement and order of standard cells and devices within an area, and the …
specifies the arrangement and order of standard cells and devices within an area, and the …
A learning-based methodology for routability prediction in placement
LC Chen, CC Huang, YL Chang… - … Symposium on VLSI …, 2018 - ieeexplore.ieee.org
The routability of a circuit is a critical challenge due to the complexity of design rules. Global
routing produces a congestion map on a coarse grid and feeds the results to the placer to …
routing produces a congestion map on a coarse grid and feeds the results to the placer to …