Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

O Marinov, MJ Deen, JA Jiménez-Tejada - Physics Reports, 2022 - Elsevier
By the continuing downscaling of sub-micron transistors in the range of few to sub-
decananometers, we focus on the increasing relative level of the low-frequency noise in …

Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications

R Chau, S Datta, A Majumdar - … Integrated Circuit Symposium …, 2005 - ieeexplore.ieee.org
This paper highlights the opportunities and challenges of III-V nanoelectronics for future high-
speed, low-power digital logic applications. III-V materials in general have significantly …

[HTML][HTML] Silicon carbide: A unique platform for metal-oxide-semiconductor physics

G Liu, BR Tuttle, S Dhar - Applied Physics Reviews, 2015 - pubs.aip.org
A sustainable energy future requires power electronics that can enable significantly higher
efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide …

[HTML][HTML] Deep level defect states in β-, α-, and ɛ-Ga2O3 crystals and films: Impact on device performance

AY Polyakov, VI Nikolaev, EB Yakimov, F Ren… - Journal of Vacuum …, 2022 - pubs.aip.org
A review is given of reported trap states in the bandgaps of different polymorphs of the
emerging ultrawide bandgap semiconductor Ga 2 O 3. The commonly observed defect …

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

T Skotnicki, JA Hutchby, TJ King… - IEEE Circuits and …, 2005 - ieeexplore.ieee.org
The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …

Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

HSP Wong, KK Chan, Y Taur - International Electron Devices …, 1997 - ieeexplore.ieee.org
In this paper, we report a fabrication method that attains the" ideal" double-gate MOSFET
device structure. The top and bottom gates are inherently self-aligned to the source/drain …

Electrical characterization of semiconductor materials and devices

MJ Deen, F Pascal - Springer Handbook of Electronic and Photonic …, 2017 - Springer
Semiconductor materials and devices continue to occupy a preeminent technological
position due to their importance when building integrated electronic systems used in a wide …

The structural factors affecting the sensory properties of polyaniline derivatives

AN Andriianova, RB Salikhov, LR Latypova… - Sustainable Energy & …, 2022 - pubs.rsc.org
Humidity control and monitoring are of great interest for a wide range of applications,
including moisture-sensitive products, storage of medicines, and environmental monitoring …

A 0.6/spl mu/m CMOS pinned photodiode color imager technology

RM Guidash, TH Lee, PPK Lee… - International …, 1997 - ieeexplore.ieee.org
The world's first submicron pinned photodiode CMOS image sensors have been produced
by adding an optimized image sensor module to a 3.3 V, 0.6/spl mu/m CMOS process. The 4 …

CMOS logic design with independent-gate FinFETs

A Muttreja, N Agarwal, NK Jha - 2007 25th International …, 2007 - ieeexplore.ieee.org
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-
scale circuits. In this paper, it is observed that in spite of improved device characteristics …