Network-on-Chips (NoCs) are becoming integral parts of modern microprocessors as the
number of cores and modules integrated on a single chip continues to increase. Research …

Until very recently, microprocessor designs were computation-centric. On-chip
communication was frequently ignored. This was because of fast, single-cycle on-chip …

We present HNOCS (Heterogeneous Network-on-Chip Simulator), an open-source NoC
simulator based on OMNeT++. To the best of our knowledge, HNOCS is the first simulator to …

As in other computer architecture areas, interconnection networks research relies most of
the times on simulation tools. This paper announces the release of an open-source tool …

The design space exploration of scaled-out manycores for communication-intensive
applications (eg, graph analytics and sparse linear algebra) is hampered due to either lack …

A new and efficient mechanism to tolerate failures ininterconnection networks for parallel
and distributedcomputers, denoted as Immunet, is presented in this work. In the presence of …

The increased demand for on-chip communication bandwidth as a result of the multi-core
trend has made networks on-chip (NoCs) a compelling choice for the communication …

The trend towards increasing the number of processor cores and cache capacity in future
Chip-Multiprocessors (CMPs), will require scalable packet-switched interconnection …

We present hornet, a parallel, highly configurable, cycle-level multicore simulator based on
an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel …

We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator
based on an ingress-queued wormhole router architecture. The parallel simulation engine …