[BOOK][B] ESL design and verification: a prescription for electronic system level methodology

G Martin, B Bailey, A Piziali - 2010 - books.google.com
Visit the authors' companion site! http://www. electronicsystemlevel. com/-Includes
interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed …

Extreme value theory for estimating task execution time bounds: A careful look

G Lima, D Dias, E Barros - 2016 28th Euromicro Conference on …, 2016 - ieeexplore.ieee.org
Extreme Value Theory (EVT) is a powerful statistical framework for estimating maximum
values of random variables and has recently been applied for deriving probabilistic bounds …

A compiler framework for the reduction of worst-case execution times

H Falk, P Lokuciejewski - Real-Time Systems, 2010 - Springer
The current practice to design software for real-time systems is tedious. There is almost no
tool support that assists the designer in automatically deriving safe bounds of the worst-case …

[BOOK][B] Processor description languages

P Mishra, N Dutt - 2011 - books.google.com
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …

Reliable Software for Unreliable Hardware

S Rehman, M Shafique, J Henkel - A Cross Layer Perspective, 2016 - Springer
vi multiple system layers in an integrated fashion for reliability optimization under user-
provided tolerable performance overhead constraints. To enable this, this work addresses …

Detecting malicious landing pages in malware distribution networks

G Wang, JW Stokes, C Herley… - 2013 43rd Annual IEEE …, 2013 - ieeexplore.ieee.org
Drive-by download attacks attempt to compromise a victim's computer through browser
vulnerabilities. Often they are launched from Malware Distribution Networks (MDNs) …

Reliability-driven software transformations for unreliable hardware

S Rehman, F Kriebel, M Shafique… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
We propose multiple reliability-driven software transformations targeting unreliable
hardware. These transformations reduce the executions of critical instructions and …

Mpsocbench: A toolset for mpsoc system level evaluation

L Duenha, M Guedes, H Almeida… - 2014 International …, 2014 - ieeexplore.ieee.org
Recent design methodologies and tools aim at enhancing the design productivity by
providing a software development platform before defining the final MPSoC architecture …

Task map** for redundant multithreading in multi-cores with reliability and performance heterogeneity

KH Chen, JJ Chen, F Kriebel, S Rehman… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
Due to the architectural design, process variations and aging, individual cores in many-core
systems exhibit heterogeneous performance. In many-core systems, a commonly adopted …

Cross-layer software dependability on unreliable hardware

S Rehman, KH Chen, F Kriebel, A Toma… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
To enable reliable embedded systems, it is imperative to leverage the compiler and system
software for joint optimization of functional correctness (ie, vulnerability indexes) and timing …