(57) ABSTRACT A data processing network includes a network of devices addressable via a
system address space, the network includ ing a computing device configured to execute an …

(57) ABSTRACT A mechanism is provided for efficient coherence state modi fication of
cached data stored in a range of addresses in a coherent data processing system in which …

A data processing system includes a memory system, a first processing element, a first
address translator that maps virtual addresses to system addresses, a second address …

A processor architecture utilizing a L3 translation lookaside buffer (TLB) to reduce page
walks. The processor includes multiple cores, where each core includes a L1 TLB and a L2 …

A processor includes a page table walk cache that stores address translation information,
and a page table walker. The page table walker fetches first output addresses indicated by …

A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the
SFA communication system comprises an SFA communicatively coupled to a plurality of …

(57) ABSTRACT A system, apparatus and method are provided in which a range of virtual
memory addresses and a copy of that range are mapped to the same first system address …

Abstract Systems and methods for managing contiguous addressing via virtual paging
registers in a page table used in a high-performance computing platform. One embodiment …

(57) ABSTRACT A host machine uses a range-based address translation system rather than
a conventional page-based system. This enables address translation to be performed with …

(57) ABSTRACT A system for providing memory access is disclosed. In some embodiments,
the system is configured to receive at a source server fabric adapter (SFA), from a server, a …