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Advanced modes in AES: Are they safe from power analysis based side channel attacks?
Advanced Encryption Standard (AES) is arguably the most popular symmetric block cipher
algorithm. The commonly used mode of operation in AES is the Electronic Codebook (ECB) …
algorithm. The commonly used mode of operation in AES is the Electronic Codebook (ECB) …
A power analysis attack resistant multicore platform with effective randomization techniques
J Yang, J Han, F Dai, W Wang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Aimed at improving the resistance against power analysis attacks, a systematic and
architectural design approach for multicore processors is proposed in this article and is …
architectural design approach for multicore processors is proposed in this article and is …
[HTML][HTML] Behavioral acoustic emanations: Attack and verification of pin entry using keypress sounds
This paper explores the security vulnerability of Personal Identification Number (PIN) or
numeric passwords. Entry Device (PEDs) that use small strings of data (PINs, keys or …
numeric passwords. Entry Device (PEDs) that use small strings of data (PINs, keys or …
Scramble suit: A profile differentiation countermeasure to prevent template attacks
Ensuring protection against side channel attacks (SCAs) is a crucial requirement in the
design of modern secure embedded systems. Profiled SCAs, the class to which template …
design of modern secure embedded systems. Profiled SCAs, the class to which template …
Side channel attacks in embedded systems: A tale of hostilities and deterrence
Security of embedded computing systems is becoming paramount as these devices become
more ubiquitous, contain personal information and are increasingly used for financial …
more ubiquitous, contain personal information and are increasingly used for financial …
SCRIP: Secure random clock execution on soft processor systems to mitigate power-based side channel attacks
Power-based side channel attacks are effective in revealing the secret keys of cryptographic
algorithm implementations running on soft processor systems. This paper, for the first time …
algorithm implementations running on soft processor systems. This paper, for the first time …
On-chip nanoscale capacitor decoupling architectures for hardware security
M Mayhew, R Muresan - IEEE Transactions on Emerging …, 2014 - ieeexplore.ieee.org
This paper presents new power analysis attack (PAA) countermeasures for nanoscale
cryptographic devices. Specifically, three circuit level architectures called partial decoupling …
cryptographic devices. Specifically, three circuit level architectures called partial decoupling …
Quadseal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks
Power based side-channel attacks attempt to obtain the secret key from implementations of
cryptographic algorithms, such as Advanced Encryption Standard (AES), by analyzing the …
cryptographic algorithms, such as Advanced Encryption Standard (AES), by analyzing the …
Design and characterisation of an AES chip embedding countermeasures
M Agoyan, S Bouquet, J Fournier… - International …, 2011 - inderscienceonline.com
In critical communication infrastructures, hardware accelerators are often used to speed up
cryptographic calculations. Their resistance to physical attacks determines how secure the …
cryptographic calculations. Their resistance to physical attacks determines how secure the …
Hardware countermeasures against power analysis attacks: a survey from past to present
R Soares, V Lima, R Lellis, P Finkenauer Jr… - Journal of Integrated …, 2021 - jics.org.br
Modern cryptographic circuits are increasingly demanding security requirements. Since its
invention, power analysis attacks are a threat to the security of such circuits. In order to …
invention, power analysis attacks are a threat to the security of such circuits. In order to …