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Methods for forming multilayer horizontal NOR-type thin-film memory strings
SB Herner, WYH Chien, J Zhou, E Harari - US Patent 11,404,431, 2022 - Google Patents
Various methods overcome the limitations and achieve supe rior scaling by (i) replacing a
single highly challenging high aspect ratio etch step with two or more etch steps of less …
single highly challenging high aspect ratio etch step with two or more etch steps of less …
Pitch-divided interconnects for advanced integrated circuit structure fabrication
AW Yeoh, A Madhavan, CP Auth - US Patent App. 15/859,415, 2019 - Google Patents
2018-03-09 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Patterning methods for semiconductor devices and structures resulting therefrom
Semiconductor devices and methods of forming semicon ductor devices are provided. A
method includes forming a first mask layer over a target layer, forming a plurality of spacers …
method includes forming a first mask layer over a target layer, forming a plurality of spacers …
Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic
FL Lie, D Shao, R Wong, Y Xu - US Patent 11,062,911, 2021 - Google Patents
First lithography and etching are carried out on a semicon ductor structure to provide a first
intermediate semiconduc tor structure having a first set of surface features correspond ing to …
intermediate semiconduc tor structure having a first set of surface features correspond ing to …
Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic
FL Lie, D Shao, R Wong, Y Xu - US Patent 10,573,528, 2020 - Google Patents
First lithography and etching are carried out on a semicon ductor structure to provide a first
intermediate semiconduc tor structure having a first set of surface features correspond ing to …
intermediate semiconduc tor structure having a first set of surface features correspond ing to …
Patterning methods for semiconductor devices and structures resulting therefrom
Semiconductor devices and methods of forming semicon ductor devices are provided. A
method includes forming a first mask layer over a target layer, forming a plurality of spacers …
method includes forming a first mask layer over a target layer, forming a plurality of spacers …
Patterning methods for semiconductor devices and structures resulting therefrom
Semiconductor devices and methods of forming semicon ductor devices are provided. A
method includes forming a first mask layer over a target layer, forming a plurality of spacers …
method includes forming a first mask layer over a target layer, forming a plurality of spacers …
Back-end-of-line compatible processing for forming an array of pillars
(57) ABSTRACT A method of forming a semiconductor structure includes forming a
memorization layer over a substrate, forming a first self-aligned double patterning (SADP) …
memorization layer over a substrate, forming a first self-aligned double patterning (SADP) …
Chemical composition for tri-layer removal
L Chen, KB Huang, NJ Yang, CW Wu… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A method includes forming a tri-layer. The tri-layer includes a bottom layer;
a middle layer over the bottom layer; and a top layer over the middle layer. The top layer …
a middle layer over the bottom layer; and a top layer over the middle layer. The top layer …
Multiple function blocks on a system on a chip (soc)
JJ Zhu, J Bao, G Nallapati - US Patent App. 17/234,377, 2022 - Google Patents
In an aspect, a system on a chip (SOC) includes a plurality of function blocks, including a first
function block and a second function block, co-located on the SOC. The SOC includes a first …
function block and a second function block, co-located on the SOC. The SOC includes a first …