Near-ultraviolet Raman and micro-Raman analysis of electronic materials
Raman and micro-Raman analysis methods have been extensively investigated for the
study of materials used in electronic and photonic devices. Raman studies are used to …
study of materials used in electronic and photonic devices. Raman studies are used to …
Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration
As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are
implemented to continue increasing performances at constant footprint. Strained and …
implemented to continue increasing performances at constant footprint. Strained and …
Source/drain eSiGe engineering for FinFET technology
Epitaxy growth loading effect—the growth rate difference between device macros due to
their local open ratio difference—is an important consideration for device design and thus …
their local open ratio difference—is an important consideration for device design and thus …
Effects of high in-situ source/drain boron do** in p-FinFETs on physical and device performance characteristics
S Shintri, C Yong, B Zhu, S Byrappa, B Fu… - Materials Science in …, 2018 - Elsevier
In this study, the effects of high in-situ boron (B) do** in embedded source/drain (S/D)
silicon germanium (SiGe) stressor of p-channel Fin Field Effect Transistors (FinFETs) in a 14 …
silicon germanium (SiGe) stressor of p-channel Fin Field Effect Transistors (FinFETs) in a 14 …
Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration
As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are
implemented to continue increasing performances at constant footprint. Strained and …
implemented to continue increasing performances at constant footprint. Strained and …
A 12nm FinFET technology featuring 2nd generation FinFET for low power and high performance applications
HC Lo, D Choi, Y Hu, Y Shen, Y Qi… - … IEEE Symposium on …, 2018 - ieeexplore.ieee.org
We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area)
improvement over 14LPP. 12LP enables> 10% area reduction including a 7.5 T library and …
improvement over 14LPP. 12LP enables> 10% area reduction including a 7.5 T library and …
Impact of 12nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level
AI Vidana, NA Dodds, RN Nowlin… - … on Nuclear Science, 2025 - ieeexplore.ieee.org
This paper presents a comparative analysis of total ionizing dose (TID) response in
GlobalFoundries' 12LP and 12LP+ 12nm bulk FinFET technologies using 10keV X-rays. Our …
GlobalFoundries' 12LP and 12LP+ 12nm bulk FinFET technologies using 10keV X-rays. Our …
Selective Epitaxial Growth of SiGe (: B) for Advanced p-Type Fd-SOI
J Lespiaux, J Kanyandekwe, T Marion, L Saidi… - ECS …, 2024 - iopscience.iop.org
We focus here on various Selective Epitaxial Growth (SEG) processes used during the
manufacturing of advanced p-MOSFET devices:(i) 20 nm thick in-situ boron doped Si0 …
manufacturing of advanced p-MOSFET devices:(i) 20 nm thick in-situ boron doped Si0 …
Germanium layer transfer and device fabrication for monolithic 3D integration
A Abedin - 2021 - diva-portal.org
Monolithic three-dimensional (M3D) integration, it has been proposed, can overcome the
limitations of further circuits' performance improvement and functionality expansion. The …
limitations of further circuits' performance improvement and functionality expansion. The …
A novel approach to control source/drain cavity profile for device performance improvement
HC Lo, J Peng, E Reis, B Zhu, W Ma… - … on Electron Devices, 2018 - ieeexplore.ieee.org
We present a novel method to form the source/drain (S/D) cavity for pFET performance
improvement—we named this cavity as do**-assisted cavity as its profile is controlled by …
improvement—we named this cavity as do**-assisted cavity as its profile is controlled by …