A review of NBTI mechanisms and models

S Mahapatra, N Parihar - Microelectronics Reliability, 2018 - Elsevier
A comprehensive review is done of different NBTI mechanisms and models proposed in the
literature over the past years. The Reaction-Diffusion (RD) model based comprehensive …

BTI analysis tool—Modeling of NBTI DC, AC stress and recovery time kinetics, nitrogen impact, and EOL estimation

N Parihar, N Goel, S Mukhopadhyay… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
A comprehensive modeling framework is presented to predict the time kinetics of negative
bias temperature instability stress and recovery during and after dc and ac stresses and also …

Modeling of NBTI kinetics in RMG Si and SiGe FinFETs, part-I: DC stress and recovery

N Parihar, RG Southwick, M Wang… - … on Electron Devices, 2018 - ieeexplore.ieee.org
An ultrafast (10-μs delay) measurement technique is used to characterize the negative bias
temperature instability-induced threshold voltage shift (ΔV T) in replacement metal gate …

[BOG][B] Fundamentals of bias temperature instability in mos transistors

S Mahapatra - 2016 - Springer
Bias Temperature Instability (BTI) is a serious reliability concern and continues to threaten
the performance and lifetime of Complementary MOS (CMOS) devices and circuits. BTI …

Modeling of NBTI using BAT framework: DC-AC stress-recovery kinetics, material, and process dependence

S Mahapatra, N Parihar - IEEE Transactions on Device and …, 2020 - ieeexplore.ieee.org
Threshold voltage shift (ΔVT) due to Negative Bias Temperature Instability (NBTI) in p-
MOSFETs is modeled using the BTI Analysis Tool (BAT) framework. The ΔV T time kinetics …

Investigations of 4H‐SiC trench MOSFET with integrated high‐K deep trench and gate dielectric

J Yao, Y Liu, A Li, X Han, Q Yao, K Yang… - IET Power …, 2024 - Wiley Online Library
This paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with
integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K …

Trap generation in IL and HK layers during BTI/TDDB stress in scaled HKMG N and P MOSFETs

S Mukhopadhyay, K Joshi, V Chaudhary… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during
NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for …

A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs

N Goel, K Joshi, S Mukhopadhyay, N Nanaware… - Microelectronics …, 2014 - Elsevier
A comprehensive modeling framework involving mutually uncorrelated contribution from
interface trap generation and hole trap** in pre-existing, process related gate insulator …

Role of oxygen vacancy in the performance variability and lattice temperature of the stacked Nanosheet FET

RK Pandey - IEEE Access, 2024 - ieeexplore.ieee.org
We have carried out a detailed study of the impact of oxygen vacancies (O), on the
performance and the lattice temperature variation in a stacked silicon nanosheet field effect …

Consistency of the two component composite modeling framework for NBTI in large and small area p-MOSFETs

A Chaudhary, B Fernandez, N Parihar… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Consistency of the recently proposed deterministic composite modeling framework for
Negative Bias Temperature Instability (NBTI) in large area devices is verified for stochastic …