Extreme ultraviolet lithography and three dimensional integrated circuit—A review
B Wu, A Kumar - Applied Physics Reviews, 2014 - pubs.aip.org
The term 3D IC generally means an IC package having multiple device layers, which is
different with 3D transistor structures such as the FinFET. 3D packaging and 3D integration …
different with 3D transistor structures such as the FinFET. 3D packaging and 3D integration …
Addressing interconnect challenges for enhanced computing performance
The advancement in semiconductor technology through the integration of more devices on a
chip has reached a point where device scaling alone is no longer an efficient way to improve …
chip has reached a point where device scaling alone is no longer an efficient way to improve …
Architecture of ring-based redundant TSV for clustered faults
WH Lo, K Chi, TT Hwang - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
Three-dimensional integrated circuits (3-D-ICs) that employ the through-silicon vias (TSVs)
vertically stacking multiple dies provide many benefits, such as high density, high …
vertically stacking multiple dies provide many benefits, such as high density, high …
Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC
Due to the rise in the number of cores in modern multicore architectures, 3-D integration (ie,
vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a …
vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a …
Design quality trade-off studies for 3-D ICs built with sub-micron TSVs and future devices
Through-silicon vias (TSVs) have two negative effects in the design of three-dimensional
integrated circuits (3-D ICs). First, TSV insertion leads to silicon area overhead. In addition …
integrated circuits (3-D ICs). First, TSV insertion leads to silicon area overhead. In addition …
Parametric studies of nanoscale through-silicon vias under the reflow in advanced packaging
L Wu, Z Liu, J Wang - Materials Science in Semiconductor Processing, 2025 - Elsevier
Nanoscale through silicon vias (nano-TSVs) has been developed for directly landing on
buried power rails (BPR), forming a backside power delivery network (BSPDN) that …
buried power rails (BPR), forming a backside power delivery network (BSPDN) that …
Design methodologies for low-power 3-D ICs with advanced tier partitioning
Low power is considered as the driving force for 3-D ICs, yet there have been few thorough
design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided …
design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided …
Modeling and simulation of a nanoscale optical computing system
Optical nanoscale computing is one promising alternative to the CMOS process. In this
paper we explore the application of Resonance Energy Transfer (RET) logic to common …
paper we explore the application of Resonance Energy Transfer (RET) logic to common …
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices
Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have
smaller footprint area, shorter wire-length, and better performance than 2D ICs. However …
smaller footprint area, shorter wire-length, and better performance than 2D ICs. However …
Fine-grained 3-D integrated circuit fabric using vertical nanowires
Continuous scaling of CMOS to sub-20nm technologies is proving to be challenging as
MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC …
MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC …