The paper presents a novel hierarchical approach to test pattern generation for sequential
circuits based on an input model of mixed-level decision diagrams. A method that handles …

A qubit method for synthesizing tests of discrete functions of SoC components is proposed,
which leverages Boolean derivatives with respect to a vector description of logic element's …

This paper addresses the problem of efficient functional simulation of synchronous digital
systems. A technique based on the use of Decision Diagrams (DD) for representing the …

This paper offers an Internet-based environment for enhancing problem-specific design
flows with test pattern generation and fault simulation capabilities. Automatic Test Pattern …

In order to cope with the complexity of today's digital systems in diagnostic modeling,
hierarchical multi-level approaches should be used. In this chapter, the possibilities of using …

Advances in design tools and methods have led to an increasing amount of design activities
being performed at higher levels of abstraction. Testability, on the other hand, is usually …

The paper proposes a new hierarchical untestable stuck-at fault identification method for
non-scan sequential circuits containing feedback loops. The method is based on deriving …

(57) ABSTRACT A single-pass method for generating test patterns for sequen tial circuits
operates upon an iterative array of time-frames representing the circuit. A map** function …

US7958421B2 - Single-pass, concurrent-validation methods for generating test patterns for
sequential circuits - Google Patents US7958421B2 - Single-pass, concurrent-validation …

The paper presents a new tool for mutation analysis using the system model of high-level
decision diagrams (HLDD). The tool is integrated into the APRICOT verification environment …