An integrated circuit device comprising a memory cell array having a plurality of memory
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …

(*) Notice: Subject to any disclaimer, the term of this “Memory Design Using a One-Transistor
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …

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Techniques for providing floating body memory devices are disclosed. In one particular
exemplary embodiment, the tech niques may be realized as a semiconductor device …

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Techniques for reducing a Voltage Swing are disclosed. In one particular exemplary
embodiment, the techniques may be realized as an apparatus for reducing a Voltage Swing …

Techniques for simultaneously driving a plurality of Source lines are disclosed. In one
particular exemplary embodiment, the techniques may be realized as an apparatus for …

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(57) ABSTRACT A semiconductor device along with circuits including the same and
methods of operating the same are described. The device comprises a memory cell …