Understanding GPU power: A survey of profiling, modeling, and simulation methods

RA Bridges, N Imam, TM Mintz - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Modern graphics processing units (GPUs) have complex architectures that admit
exceptional performance and energy efficiency for high-throughput applications. Although …

Software tools for microalgae biorefineries: Cultivation, separation, conversion process integration, modeling, and optimization

AA Kasani, A Esmaeili, A Golzary - Algal Research, 2022 - Elsevier
In the operation of biorefineries, performing a quantitative, economic, and environmental
assessment of process equipment design without the use of related software, is time …

Barra: A parallel functional simulator for gpgpu

C Collange, M Daumas, D Defour… - 2010 IEEE International …, 2010 - ieeexplore.ieee.org
We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general
purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the …

Profiling attacker behavior following SSH compromises

D Ramsbrock, R Berthier… - 37th Annual IEEE/IFIP …, 2007 - ieeexplore.ieee.org
This practical experience report presents the results of an experiment aimed at building a
profile of attacker behavior following a remote compromise. For this experiment, we utilized …

Fast virtual prototy** for embedded computing systems design and exploration

A Charif, G Busnot, R Mameesh, T Sassolas… - Proceedings of the …, 2019 - dl.acm.org
Virtual Prototy** has been widely adopted as a cost-effective solution for early hardware
and software co-validation. However, as systems grow in complexity and scale, both the time …

SoCRocket-A virtual platform for the European Space Agency's SoC development

T Schuster, R Meyer, R Buchty… - … -Centric Systems-on …, 2014 - ieeexplore.ieee.org
SoCRocket is a design framework for rapid SoC development. Emerged from an industrial
case study for the European Space Agency (ESA) it enables design, verification and …

Using binary translation in event driven simulation for fast and flexible MPSoC simulation

M Gligor, N Fournel, F Pétrot - Proceedings of the 7th IEEE/ACM …, 2009 - dl.acm.org
In this paper, we investigate the use of instruction set simulators (ISS) based on binary
translation to accelerate full timed multiprocessor system simulation at transaction level. To …

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

I Böhm, B Franke, N Topham - 2010 International Conference …, 2010 - ieeexplore.ieee.org
Instruction set simulators (ISS) are vital tools for compiler and processor architecture design
space exploration and verification. State-of-the-art simulators using just-in-time (JIT) …

Multilevel simulation-based co-design of next generation HPC microprocessors

L Zaourar, M Benazouz, A Mouhagir… - … and Simulation of …, 2021 - ieeexplore.ieee.org
This paper demonstrates the combined use of three simulation tools in support of a co-
design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation …

A formal design framework to generate coprocessors with implementation options

MF Dossis - International Journal of Research and Reviews in …, 2011 - search.proquest.com
This paper describes a formal high-level synthesis design framework which is used to
automatically generate provably-correct coprocessor, implementable hardware descriptions …