Ultimately thin double-gate SOI MOSFETs
The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate
(SG) mode (for either front or back channel), is systematically analyzed. Strong interface …
(SG) mode (for either front or back channel), is systematically analyzed. Strong interface …
Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs
L Ge, JG Fossum - IEEE Transactions on Electron Devices, 2002 - ieeexplore.ieee.org
A compact physics-based quantum-effects model for symmetrical double-gate (DG)
MOSFETs of arbitrary Si-film thickness is developed and demonstrated. The model, based …
MOSFETs of arbitrary Si-film thickness is developed and demonstrated. The model, based …
Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
K Kim, JG Fossum - IEEE Transactions on Electron Devices, 2001 - ieeexplore.ieee.org
Numerical device-simulation results, supplemented by analytical characterizations, are
presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup+/and …
presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup+/and …
Electronics below 10 nm
K Likharev - Nano and giga challenges in microelectronics, 2003 - Elsevier
Publisher Summary The aim of this chapter is to review the prospects for the development
and practical introduction of ultra small electron devices, including nanoscale field-effect …
and practical introduction of ultra small electron devices, including nanoscale field-effect …
FinFET SRAM design
R Joshi, K Kim, R Kanj - Nanoelectronic Circuit Design, 2011 - Springer
We present a comprehensive review of finFET devices taking into consideration different
levels of interest ranging from the physics of FinFET devices, design considertaions, and …
levels of interest ranging from the physics of FinFET devices, design considertaions, and …
Nanoscale silicon MOSFETs: A theoretical study
VA Sverdlov, TJ Walls… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
We have carried out extensive numerical modeling of double-gate, nanoscale silicon n-
metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic …
metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic …
Investigation on variability in metal-gate Si nanowire MOSFETs: Analysis of variation sources and experimental characterization
The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-
semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated …
semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated …
Electrical performance optimization of nanoscale double-gate MOSFETs using multiobjective genetic algorithms
In this paper, a new multiobjective genetic algorithm (MOGA)-based approach is proposed
to optimize the electrical performance of double-gate (DG) MOSFETs for nanoscale CMOS …
to optimize the electrical performance of double-gate (DG) MOSFETs for nanoscale CMOS …
[LIVRE][B] Nanometer Cmos
This book presents the material necessary for understanding the physics, operation, design,
and performance of modern MOSFETs with nanometer dimensions. It offers a brief …
and performance of modern MOSFETs with nanometer dimensions. It offers a brief …
Physics-based compact model of nanoscale MOSFETs-Part I: transition from drift-diffusion to ballistic transport
G Mugnaini, G Iannaccone - IEEE Transactions on Electron …, 2005 - ieeexplore.ieee.org
In this paper, we present a physics-based analytical model for nanoscale MOSFETs that
allows us to seamlessly cover the whole range of regimes from drift-diffusion (DD) to ballistic …
allows us to seamlessly cover the whole range of regimes from drift-diffusion (DD) to ballistic …