A Review of Advancements and Trends in Time-to-Digital Converters Based on FPGA

H **a, X Yu, J Zhang, G Cao - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Recently, advancements have been made in the design, implementation, and application of
time-to-digital converters (TDCs) based on field-programmable gate array (FPGA) …

[HTML][HTML] Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review

D Real, D Calvo - Sensors, 2024 - mdpi.com
A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented
within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection …

Ultra compact pulse shrinking TDC on FPGA

L **ang, P Yang, T Wu, M Zhou - Measurement, 2022 - Elsevier
This study propose a new design of a field-programmable gate array (FPGA) based pulse
shrinking time-to-digital converter (TDC), where only several configuration logic block (CLB) …

A High-Precision Folding Time-to-Digital Converter Implemented in Kintex-7 FPGA

Y Zhou, Y Wang, Z Song, X Kong - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Time-to-digital converters (TDCs) based on field-programmable gate array (FPGA) generally
use a tapped delay line (TDL) to propagate the hit signal for time interpolation within one …

A high-throughput vernier time-to-digital converter on FPGAs with improved resolution using a bi-time interpolation scheme

G Xu, B Zha, T **a, Z Zheng, H Zhang - Applied Sciences, 2022 - mdpi.com
A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-
timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to …

A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 N· m FGPAs

Y Wang, W **e, H Chen, C Pei… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This article presents a two-stage interpolation time-to-digital converter (TDC), combining a
Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL-TDC) …

Single measurement wave union time-to-digital converter with a subsampling-scheme-based codification

M Arredondo-Velázquez, R Guadarrama… - Nuclear Instruments and …, 2025 - Elsevier
The prevalent hardware architecture used in time-to-digital converters consists of a tapped
delay line, a capture module, and an encoder. Recent trends indicate a growing interest in …

A Compact Upconversion Single-Photon Imager for Full-Range and Accurate 3-D Imaging

Y Chen, C Jiang, Y Liu, H Su, X Hu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The rapid development of single-photon detection technology offers the possibility for an
imaging system to go beyond traditional limits. Recently, single-photon imagers based on …

High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA

L Castelvero, IHL Grande, V Pruneri - IEEE Access, 2024 - ieeexplore.ieee.org
In recent years, field-programmable gate arrays (FPGAs) have emerged as promising
platforms for implementing picosecond-resolution time-to-digital converters (TDCs). Tapped …

A 64× 64 Gated-SPAD Image Sensor with 2D and 3D Imaging Using a Time domain Sampling Histogram

H Shi, D Li, R Ma, Z Zhu - IEEE Transactions on Instrumentation …, 2024 - ieeexplore.ieee.org
A proof-of-concept prototype is presented, which can be used for 2D and 3D imaging with a
resolution of 64x64, and it consists of a 110nm complementary metal oxide semiconductor …