Low‐latency median filter core for hardware implementation of 5× 5 median filtering
This study presents hardware implementation of 5× 5 median filter that uses a new low‐
latency median filter (LLMF) core in order to find the median of 25 integer values. The …
latency median filter (LLMF) core in order to find the median of 25 integer values. The …
Fast median‐finding word comparator array
J Subramaniam, JK Raju, D Ebenezer - Electronics Letters, 2017 - Wiley Online Library
Finding the median of a set of data within a window of finite size is computationally
challenging on account of the complexity in sorting. Compared with the established nine …
challenging on account of the complexity in sorting. Compared with the established nine …
A new fast and efficient 2-D median filter architecture
Existing architectures for the median filter are based on sorting algorithm where comparators
are used in serial. This paper proposes a new high-speed architecture of two dimensional (2 …
are used in serial. This paper proposes a new high-speed architecture of two dimensional (2 …
Parallel and pipelined 2-D median filter architecture
J Subramaniam, RJ Kannan… - IEEE Embedded …, 2017 - ieeexplore.ieee.org
The existing 2-D median filters in the literature are computationally intensive. It is proposed
to optimally reduce the amount of data handled at the architecture level realization of the …
to optimally reduce the amount of data handled at the architecture level realization of the …
VLSI Implementation of an Efficient 2D Median Finding Algorithm for Non Linear Image Filtering
K Vasanth, MC Nithin, SD ALN… - … on Circuit Power …, 2024 - ieeexplore.ieee.org
This paper proposes an efficient architecture of two dimensional (2-D) Modified shear
sorting architecture which produces median output based on pixels given in a window of MX …
sorting architecture which produces median output based on pixels given in a window of MX …
VLSI implementation of high throughput parallel pipeline median finder for IoT applications
This paper proposes a high-throughput median finding architecture where the sorting of an
incoming pixel is executed by a high-speed Compare and Select (CS) module. In this work …
incoming pixel is executed by a high-speed Compare and Select (CS) module. In this work …
An FPGA Implementation of an Impulse Noise Reduction Algorithm in Visual Sensor Network
MR Lone - Circuits, Systems, and Signal Processing, 2022 - Springer
In this paper, nearest neighbor filtering method is presented for impulse noise reduction. If a
pixel is corrupted by impulse noise, nearest non-noisy pixel can be a better option to replace …
pixel is corrupted by impulse noise, nearest non-noisy pixel can be a better option to replace …
Design and analysis of imaging chip using high-speed AXI-interface for MPSOC applications on FPGA platform
HR Archana, CRB Reddy - Wireless Personal Communications, 2024 - Springer
The recent innovations in real-time video and image enhancements are allowing much
advancement in a wide range of diverse applications. These innovations and advancements …
advancement in a wide range of diverse applications. These innovations and advancements …
An fpga realization for real-time depth estimation in image sequences
This paper proposes a method for depth estimation in video sequences acquired by a
monocular camera mounted on a mobile platform. The proposed algorithm is able to …
monocular camera mounted on a mobile platform. The proposed algorithm is able to …
[PDF][PDF] Design of Low Power Architecture for Approximate Parallel Mid-Point Filter
NKJP Thiagarajan, KN Vijeyakumar, S Saravanakumar - 2022 - scholar.archive.org
Approximate computing is a modern techniques for design of low power efficient arithmetic
circuits for portable error resilient applications. In this work, we have proposed a Adaptive …
circuits for portable error resilient applications. In this work, we have proposed a Adaptive …