The cost of application-class processing: Energy and performance analysis of a Linux-ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology

F Zaruba, L Benini - IEEE Transactions on Very Large Scale …, 2019 - ieeexplore.ieee.org
The open-source RISC-V instruction set architecture (ISA) is gaining traction, both in industry
and academia. The ISA is designed to scale from microcontrollers to server-class …

FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud

S Karandikar, H Mao, D Kim, D Biancolin… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
We present FireSim, an open-source simulation platform that enables cycle-exact
microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated …

A survey on run-time power monitors at the edge

D Zoni, A Galimberti, W Fornaciari - ACM Computing Surveys, 2023 - dl.acm.org
Effectively managing energy and power consumption is crucial to the success of the design
of any computing system, hel** mitigate the efficiency obstacles given by the downsizing …

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations

A Izraelevitz, J Koenig, P Li, R Lin… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
Enabled by modern languages and retargetable compilers, software development is in a
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …

GRANNITE: Graph neural network inference for transferable power estimation

Y Zhang, H Ren, B Khailany - 2020 57th ACM/IEEE Design …, 2020 - ieeexplore.ieee.org
This paper introduces GRANNITE, a GPU-accelerated novel graph neural network (GNN)
model for fast, accurate, and transferable vector-based average power estimation. During …

RFUZZ: Coverage-directed fuzz testing of RTL on FPGAs

K Laeufer, J Koenig, D Kim… - 2018 IEEE/ACM …, 2018 - ieeexplore.ieee.org
Dynamic verification is widely used to increase confidence in the correctness of RTL circuits
during the pre-silicon design phase. Despite numerous attempts over the last decades to …

Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V SoC on FireSim

F Farshchi, Q Huang, H Yun - 2019 2nd Workshop on Energy …, 2019 - ieeexplore.ieee.org
NVDLA is an open-source deep neural network (DNN) accelerator which has received a lot
of attention by the community since its introduction by Nvidia. It is a full-featured hardware IP …

Simmani: Runtime power modeling for arbitrary RTL with automatic signal selection

D Kim, J Zhao, J Bachrach, K Asanović - … of the 52nd Annual IEEE/ACM …, 2019 - dl.acm.org
This paper presents a novel runtime power modeling methodology which automatically
identifies key signals for power dissipation of any RTL design. The toggle-pattern matrix is …

[PDF][PDF] Power and Energy Characterization of an Open Source 25-Core Manycore Processor.

M McKeown, A Lavrov, M Shahrad, PJ Jackson, Y Fu… - HPCA, 2018 - princeton.edu
The end of Dennard's scaling and the looming power wall have made power and energy
primary design goals for modern processors. Further, new applications such as cloud …

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation

K Zhou, Y Liang, Y Lin, R Wang, R Huang - … of the 56th Annual IEEE/ACM …, 2023 - dl.acm.org
The use of register transfer level (RTL) simulation is critical for hardware design in various
aspects including verification, debugging, and design space exploration. Among various …