The cost of application-class processing: Energy and performance analysis of a Linux-ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology
The open-source RISC-V instruction set architecture (ISA) is gaining traction, both in industry
and academia. The ISA is designed to scale from microcontrollers to server-class …
and academia. The ISA is designed to scale from microcontrollers to server-class …
FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud
We present FireSim, an open-source simulation platform that enables cycle-exact
microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated …
microarchitectural simulation of large scale-out clusters by combining FPGA-accelerated …
A survey on run-time power monitors at the edge
Effectively managing energy and power consumption is crucial to the success of the design
of any computing system, hel** mitigate the efficiency obstacles given by the downsizing …
of any computing system, hel** mitigate the efficiency obstacles given by the downsizing …
Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
Enabled by modern languages and retargetable compilers, software development is in a
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …
GRANNITE: Graph neural network inference for transferable power estimation
This paper introduces GRANNITE, a GPU-accelerated novel graph neural network (GNN)
model for fast, accurate, and transferable vector-based average power estimation. During …
model for fast, accurate, and transferable vector-based average power estimation. During …
RFUZZ: Coverage-directed fuzz testing of RTL on FPGAs
Dynamic verification is widely used to increase confidence in the correctness of RTL circuits
during the pre-silicon design phase. Despite numerous attempts over the last decades to …
during the pre-silicon design phase. Despite numerous attempts over the last decades to …
Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V SoC on FireSim
NVDLA is an open-source deep neural network (DNN) accelerator which has received a lot
of attention by the community since its introduction by Nvidia. It is a full-featured hardware IP …
of attention by the community since its introduction by Nvidia. It is a full-featured hardware IP …
Simmani: Runtime power modeling for arbitrary RTL with automatic signal selection
This paper presents a novel runtime power modeling methodology which automatically
identifies key signals for power dissipation of any RTL design. The toggle-pattern matrix is …
identifies key signals for power dissipation of any RTL design. The toggle-pattern matrix is …
[PDF][PDF] Power and Energy Characterization of an Open Source 25-Core Manycore Processor.
The end of Dennard's scaling and the looming power wall have made power and energy
primary design goals for modern processors. Further, new applications such as cloud …
primary design goals for modern processors. Further, new applications such as cloud …
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation
The use of register transfer level (RTL) simulation is critical for hardware design in various
aspects including verification, debugging, and design space exploration. Among various …
aspects including verification, debugging, and design space exploration. Among various …