Data center energy consumption modeling: A survey

M Dayarathna, Y Wen, R Fan - IEEE Communications surveys …, 2015 - ieeexplore.ieee.org
Data centers are critical, energy-hungry infrastructures that run large-scale Internet-based
services. Energy consumption models are pivotal in designing and optimizing energy …

Exploring exploration: A tutorial introduction to embedded systems design space exploration

AD Pimentel - IEEE Design & Test, 2016 - ieeexplore.ieee.org
As embedded systems grow more complex and as new applications such as IoT require
many design constraints, sophisticated design space exploration techniques are essential in …

The gem5 simulator: Version 20.0+

J Lowe-Power, AM Ahmad, A Akram, M Alian… - arxiv preprint arxiv …, 2020 - arxiv.org
The open-source and community-supported gem5 simulator is one of the most popular tools
for computer architecture research. This simulation infrastructure allows researchers to …

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

A Farmahini-Farahani, JH Ahn… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Energy consumed for transferring data across the processor memory hierarchy constitutes a
large fraction of total system energy consumption, and this fraction has steadily increased …

Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation

K Hsieh, S Khan, N Vijaykumar… - 2016 IEEE 34th …, 2016 - ieeexplore.ieee.org
Pointer chasing is a fundamental operation, used by many important data-intensive
applications (eg, databases, key-value stores, graph processing workloads) to traverse …

Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems

H Asghari-Moghaddam, YH Son… - 2016 49th annual …, 2016 - ieeexplore.ieee.org
The performance of computer systems is often limited by the bandwidth of their memory
channels, but further increasing the bandwidth is challenging under the stringent pin and …

Memory-centric system interconnect design with hybrid memory cubes

G Kim, J Kim, JH Ahn, J Kim - Proceedings of the 22nd …, 2013 - ieeexplore.ieee.org
Memory bandwidth has been one of the most critical system performance bottlenecks. As a
result, the HMC (Hybrid Memory Cube) has recently been proposed to improve DRAM …

SPARTA: Runtime task allocation for energy efficient heterogeneous many-cores

B Donyanavard, T Mück, S Sarma, N Dutt - Proceedings of the Eleventh …, 2016 - dl.acm.org
To meet the performance and energy efficiency demands of emerging complex and variable
workloads, heterogeneous many-core architectures are increasingly being deployed …

Quantifying sources of error in McPAT and potential impacts on architectural studies

SL **, H Jacobson, P Bose, GY Wei… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Architectural power modeling tools are widely used by the computer architecture community
for rapid evaluations of high-level design choices and design space explorations. Currently …

Reducing memory access latency with asymmetric DRAM bank organizations

YH Son, O Seongil, Y Ro, JW Lee, JH Ahn - Proceedings of the 40th …, 2013 - dl.acm.org
DRAM has been a de facto standard for main memory, and advances in process technology
have led to a rapid increase in its capacity and bandwidth. In contrast, its random access …