Insights into the DC, RF/Analog and linearity performance of vertical tunneling based TFET for low-power applications

N Paras, SS Chauhan - Microelectronic Engineering, 2019 - Elsevier
The concept of dual metal and double gate in Vertical TFET is presented to show the
improvement of DC as well as analog/RF device performance standards due to enhanced …

Use of metal strip in stacked gate oxide JLTFET improves device quality and single-event-transient effect

A Vanak, A Amini - Materials Science and Engineering: B, 2024 - Elsevier
This study represents a stacked gate oxide junctionless tunneling field effect transistor
(JLTFET) which has metal strips in gate oxide layers. The metal strips make improvement in …

Triple metal extended source double gate vertical TFET with boosted DC and analog/RF performance for low power applications

P Karmakar, P Patil, PK Sahu - Silicon, 2022 - Springer
A vertical tunnel FET with triple metal and stacked hetero gate dielectric oxide is proposed.
In the structure, the gate imbricates the source. Amid the source section and the gate oxide …

Modified gate oxide double gate tunnel field-effect transistor

P Karmakar, PK Sahu - Silicon, 2022 - Springer
This paper proposes a unique Tunnel Field-Effect Transistor (TFET) structure in which the
gate oxide is modified, and the performances of the device are analyzed using Sentaurus …

Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study

S Das, A Chattopadhyay… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, for the first time, an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a
unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and …

Improvements in reliability and radio frequency performance of junctionless tunnelling field effect transistor using p+ pocket and metal strip

A Zirak - IET Circuits, Devices & Systems, 2023 - Wiley Online Library
In this article, a new p+ pocket stacked gate oxide junctionless tunnelling field effect
transistor (junction less tunnelling field effect transistor (JLTFET)) which has metal strip in …

Analytical modeling and simulation of a triple-material double-gate SON TFET with stacked front-gate oxide for low-power applications

K Eyvazi, MA Karami - Iranian Journal of Science and Technology …, 2023 - Springer
This paper proposes a two-dimensional analytical model of a triple-material double-gate
silicon-on-nothing tunnel field-effect transistor (TM-DG SON TFET) with stacked front-gate …

Improvements in Reliability and RF Performance of Stacked Gate JLTFET Using p+ Pocket and Heterostructure Material

A Vanak, A Amini, SH Pishgar - Silicon, 2023 - Springer
In this paper, a new p+ pocket heterostructure stacked gate junction-less tunneling field
effect transistor (JLTFET) is proposed. The simulation results indicate that, the proposed …

A new Junction-Less Tunnel Field-Effect Transistor with a SiO2/HfO2 stacked gate oxide for DC performance improvement

K Eyvazi, MA Karami - 2020 28th Iranian Conference on …, 2020 - ieeexplore.ieee.org
In this paper, a Junction-Less Tunnel Field-Effect Transistor (JLTFET) with a SiO 2/HfO 2
stacked gate oxide is proposed for steep average subthreshold swing (SS avg) and high ON …

TCAD performance analysis of PIN tunneling FETS under surrounded gate structure

R Dutta, N Paitya - 2nd international conference on advances in …, 2019 - papers.ssrn.com
In this paper, an attempt has been made to get high drive current (ION) for tunnel FETs by
comparing conventional double gate tunnel field effect transistor (DG-TFET) with double …