A strategic review on gallium oxide based power electronics: Recent progress and future prospects

D Kaur, A Ghosh, M Kumar - Materials Today Communications, 2022‏ - Elsevier
Silicon based power devices have limited capabilities in terms of voltage handling and
switching speeds, leading to rampant research in the field of next generation wide bandgap …

Germanium surface passivation and atomic layer deposition of high-k dielectrics—a tutorial review on Ge-based MOS capacitors

Q **e, S Deng, M Schaekers, D Lin… - Semiconductor …, 2012‏ - iopscience.iop.org
Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel
material (offering a mobility gain of approximately× 2 for electrons and× 4 for holes when …

Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces

R Engel-Herbert, Y Hwang, S Stemmer - Journal of applied physics, 2010‏ - pubs.aip.org
Methods to extract trap densities at high-permittivity (k) dielectric/III-V semiconductor
interfaces and their distribution in the semiconductor band gap are compared. The …

III–V compound semiconductor transistors—from planar to nanowire structures

H Riel, LE Wernersson, M Hong, JA Del Alamo - Mrs Bulletin, 2014‏ - cambridge.org
Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic
device roadmap to further improve future performance increases of integrated circuits is …

Interface states in gate stack of carbon nanotube array transistors

Y Liu, S Ding, W Li, Z Zhang, Z Pan, Y Ze, B Gao… - ACS …, 2024‏ - ACS Publications
A deep understanding of the interface states in metal–oxide–semiconductor (MOS)
structures is the premise of improving the gate stack quality, which sets the foundation for …

A Distributed Model for Border Traps in MOS Devices

Y Yuan, L Wang, B Yu, B Shin, J Ahn… - IEEE Electron …, 2011‏ - ieeexplore.ieee.org
A distributed border trap model based on tunneling between the semiconductor surface and
trap states in the gate dielectric film is formulated to account for the observed frequency …

Interface State Density in Atomic Layer Deposited SiO2/ -Ga2O3 ( ) MOSCAPs

K Zeng, Y Jia, U Singisetti - IEEE Electron Device Letters, 2016‏ - ieeexplore.ieee.org
The interface state density (D it) at the interface between β-Ga 2 O 3 (2̅01) and atomic layer
deposited (ALD) SiO 2 dielectric is extracted using Terman method and conductance …

A Distributed Bulk-Oxide Trap Model for InGaAs MOS Devices

Y Yuan, B Yu, J Ahn, PC McIntyre… - … on Electron Devices, 2012‏ - ieeexplore.ieee.org
This paper presents a distributed circuit model for bulk-oxide traps based on tunneling
between the semiconductor surface and trap states in the gate dielectric film. The model is …

Interfacial chemistry of oxides on InxGa (1− x) As and implications for MOSFET applications

CL Hinkle, EM Vogel, PD Ye, RM Wallace - Current Opinion in Solid State …, 2011‏ - Elsevier
The prospect of enhanced device performance from III–V materials has been recognized for
at least 50years, and yet, relative to the phenomenal size of the Si-based IC industry, these …

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to and InP Capacitors

G Brammertz, A Alian, DHC Lin… - … on Electron Devices, 2011‏ - ieeexplore.ieee.org
By taking into account simultaneously the effects of border traps and interface states, the
authors model the alternating current capacitance-voltage (CV) behavior of high-mobility …