Development and challenges of reliability modeling from transistors to circuits

X Yang, Q Sang, C Wang, M Yu… - IEEE Journal of the …, 2023 - ieeexplore.ieee.org
The integration density of electronic systems is limited by the reliability of the integrated
circuits. To guarantee the overall performance, the integrated circuit reliability must be …

[HTML][HTML] Recent progress in physics-based modeling of electromigration in integrated circuit interconnects

WS Zhao, R Zhang, DW Wang - Micromachines, 2022 - mdpi.com
The advance of semiconductor technology not only enables integrated circuits with higher
density and better performance but also increases their vulnerability to various aging …

Transistor self-heating: The rising challenge for semiconductor testing

O Prakash, CK Dabhi, YS Chauhan… - 2021 IEEE 39th VLSI …, 2021 - ieeexplore.ieee.org
Quantum confinement in 3-D device structure together with the newly employed materials
like silicon-germanium (SiGe) in advanced technologies (eg, FinFET, nanowire, nanosheets …

Impact of interface traps on negative capacitance transistor: Device and circuit reliability

O Prakash, A Gupta, G Pahwa, J Henkel… - IEEE Journal of the …, 2020 - ieeexplore.ieee.org
In this work, we investigate the impact of Si-SiO 2 interface traps on the performance of
negative capacitance transistor, which is a promising emerging technology that aims at …

Scalable machine learning to estimate the impact of aging on circuits under workload dependency

F Klemme, H Amrouch - … Transactions on Circuits and Systems I …, 2022 - ieeexplore.ieee.org
To ensure the correct functionality of a chip throughout its entire lifetime, preliminary circuit
analysis with respect to aging-induced degradation is indispensable. However, state-of-the …

Efficient learning strategies for machine learning-based characterization of aging-aware cell libraries

F Klemme, H Amrouch - … Transactions on Circuits and Systems I …, 2022 - ieeexplore.ieee.org
Machine learning (ML)-driven standard cell library characterization enables rapid, on-the-fly
generation of cell libraries, opening the door for extensive design-space exploration and …

Upheaving self-heating effects from transistor to circuit level using conventional EDA tool flows

F Klemme, S Salamin… - 2023 Design, Automation & …, 2023 - ieeexplore.ieee.org
In this work, we are the first to demonstrate how well-established EDA tool flows can be
employed to upheave Self-Heating Effects (SHE) from individual devices at the transistor …

Machine learning for circuit aging estimation under workload dependency

F Klemme, H Amrouch - 2021 IEEE International Test …, 2021 - ieeexplore.ieee.org
Circuit analysis with respect to aging-induced degradation is critical to ensure correct
operation throughout the entire lifetime of a chip. However, state-of-the-art techniques only …

Aging-aware gate-level modeling for circuit reliability analysis

Z Zhang, R Wang, X Shen, D Wu… - … on Electron Devices, 2021 - ieeexplore.ieee.org
Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight
for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In …

Toward security closure in the face of reliability effects iccad special session paper

J Lienig, S Rothe, M Thiele… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
The reliable operation of ICs is subject to physical effects like electromigration, thermal and
stress migration, negative bias temperature instability, hot-carrier injection, etc. While these …