Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits
have broad application prospects in large-scale flexible electronics. To simplify circuit …

Process variability, in addition to wide temperature and supply voltage variation ranges,
severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of …

This paper presents a fast and efficient optimization engine with multi-directional, multi-
objective algorithms based on a robust transistor sizing approach to improve digital circuit …

The increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit
fabrication favor the flourishing of emerging technologies. Because of their limited sizes …

We present the detailed results of the application of mathematical optimization algorithms to
transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield …

In recent decades, near-threshold voltage (NTV) design has become a well-known
technique for improving the energy efficiency of digital integrated circuits. However, scaling …

The primary goal of this research paper is to examine the impact of different design
parameters on the power-delay product (PDP) in low-power very-large-scale integration …

In this paper, we present a multi-objective optimisation technique for transistor sizing in the
variation-prone nanometric complementary metal-oxide semiconductor (CMOS) logic cells …

In this paper, we present mathematical models of the failure probabilities of individual MOS
transistors. We use the models to characterize the failures of a few common CMOS logic …

In this paper, we propose a technique for concurrent optimization of CMOS logic gates for
power-and-noisemargin and energy-and-noise-margin. The role of progressive sizing for …