Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to
combine sensing and computing within a single chip. A special characteristic of …

Emerging 3D integrated circuits (ICs) employ 3D network-on-chip (NoC) to improve power,
performance, and scalability. The NoC Simulator uses the microarchitecture parameters to …

The article gives a review of existing methods of network-on-chip design based on the
approach in which map** of the characteristic tasks graph is performed on a given regular …

For analytically defined families of three-dimensional circulant networks with a parametric
description, an analytical algorithm for finding shortest paths which has a common scheme …

We introduce ratatoskr, an open-source framework for in-depth power, performance and
area (PPA) analysis in NoCs for 3D-integrated and heterogeneous System-on-Chips …

In this chapter, we discuss the basics of interconnect architectures for 2D and 3D SoCs. The
trend toward more components in a SoC requires an interconnect architecture whose …

An approach for constructing and optimizing graphs of series of analytically described
circulant graphs of degree six with general topological properties is proposed. The paper …

A network on a chip is a solitary silicon chip utilized to perform the communication
characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network …

For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip
(SoC), the locations of components, routers and vertical links are determined from an …

3D heterogeneous integration poses new requirements to the modeling of interconnection
networks. Traditional simulation models for Networks-on-Chip (NoCs) cover neither …