Parallel implementation of genetic algorithm on FPGA using Vivado high level synthesis

E Alqudah, A Jarrah - International Journal of Bio-Inspired …, 2020 - inderscienceonline.com
Genetic algorithm (GA) is one of most popular evolutionary search algorithms that simulates
natural selection of genetic evolution for searching solution to arbitrary engineering …

Designing energy-efficient approximate adders using parallel genetic algorithms

AA Naseer, RA Ashraf, D Dechev… - SoutheastCon …, 2015 - ieeexplore.ieee.org
Approximate computing involves selectively reducing the number of transistors in a circuit to
improve energy savings. Energy savings may be achieved at the cost of reduced accuracy …

Fast and Scalable Design Space Exploration for Deep Learning on Embedded Systems

B Kutukcu, S Baidya, S Dey - IEEE Access, 2024 - ieeexplore.ieee.org
Deep learning algorithms are used in various advanced applications, including computer
vision, large language models and many others due to their increasing success over …

Bangla grammar pattern recognition using shift reduce parser

RZ Rabbi, MIR Shuvo… - 2016 5th International …, 2016 - ieeexplore.ieee.org
Parser plays a very important role in computational linguistics. In this paper, here we
describe a parsing technique for Bangla grammar recognition. The parser is, by nature, a …

Towards trust hardware deployment of edge computing: mitigation of hardware trojans based on evolvable hardware

Z Li, J Wang, Z Huang, N Luo, Q Wang - Applied Sciences, 2022 - mdpi.com
Hardware Trojans (HTs) are malicious hardware components designed to leak confidential
information or cause the chip/circuit on which they are integrated to malfunction during …

A Genetic Algorithm for Combinational Logic Circuit Synthesis Using Directed Graph Primitives

RC Yarnell, P Powell, RF DeMara… - … Conference on Machine …, 2023 - ieeexplore.ieee.org
We introduce functionality-cognizant Genetic Algorithms (GAs) and graph-based operators
to tackle the challenging search landscape of combinational digital circuit design. We …

Enabling Deep Learning Inference on Resource Constrained Devices

B Kutukcu - 2024 - escholarship.org
This study aims to enable deep learning models on resource constrained devices
considering system and application requirements. The proven success of deep learning …

The dynamic evaluation strategy for evolvable hardware

J Wang, J Liu, B Feng, G Hou - 2015 Ninth International …, 2015 - ieeexplore.ieee.org
Evolvable hardware (EHW) has recently become a highly attractive topic for the Fault-
tolerant System design because it offers a way of adapting hardware to different …

[PDF][PDF] Indexed bibliography of genetic algorithms & evolvable hardware and FPGAs

JT Alander - 1994 - researchgate.net
An Indexed Bibliography of Genetic Algorithms & Evolvable Hardware and FPGAs Page 1
An Indexed Bibliography of Genetic Algorithms & Evolvable Hardware and FPGAs compiled …

Assessing Approximate Arithmetic Designs in the presence of Process Variations and Voltage Scaling

AA Naseer - 2015 - stars.library.ucf.edu
As environmental concerns and portability of electronic devices move to the forefront of
priorities, innovative approaches which reduce processor energy consumption are sought …