Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design
A physically based compact analytical single electron transistor (SET) model is proposed for
hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the" …
hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the" …
Realization of multiple valued logic and memory by hybrid SETMOS architecture
A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET)
hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade …
hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade …
On-chip optical interconnect for low-power
It is an accepted fact that process scaling and operating frequency both contribute to
increasing integrated circuit power dissipation due to interconnect. Extrapolating this trend …
increasing integrated circuit power dissipation due to interconnect. Extrapolating this trend …
Influence of quantum dot characteristics on the performance of hybrid SET-FET circuits
Quantum dots (QDs) can be used as conductive islands to build-up single-electron
transistors (SETs). The characteristics of the QDs define the functional performance of the …
transistors (SETs). The characteristics of the QDs define the functional performance of the …
Analog-digital and digital-analog converters using single-electron and MOS transistors
X Ou, NJ Wu - IEEE transactions on nanotechnology, 2005 - ieeexplore.ieee.org
This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and
digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and …
digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and …
3-D design and analysis of functional NEMS-gate MOSFETs and SETs
B Pruvost, H Mizuta, S Oda - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Nanoelectromechanical system (NEMS)-gate metal-oxide-semiconductor field effect
transistor (MOSFET) and single-electron transistor (SET) structures are investigated by …
transistor (MOSFET) and single-electron transistor (SET) structures are investigated by …
Binary multiplication using hybrid MOS and multi-gate single-electron transistors
G Deng, C Chen - IEEE transactions on very large scale …, 2012 - ieeexplore.ieee.org
In this paper, we investigate the design of binary tree multipliers based on multi-input
counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the …
counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the …
300 K operating full-CMOS integrated single electron transistor (SET)-FET circuits
We demonstrate the first Single Electron Transistor (SET) with high-k/metal gate operating at
room temperature (at VD= 0.9 V) cointegrated with fully depleted SOI (FDSOI) MOSFET (with …
room temperature (at VD= 0.9 V) cointegrated with fully depleted SOI (FDSOI) MOSFET (with …
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities
For the first time we evidence the transition from a MOSFET operation to Single Electron
Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper …
Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper …
SET/CMOS hybrid process and multiband filtering circuits
KW Song, YK Lee, JS Sim, H Jeoung… - IEEE transactions on …, 2005 - ieeexplore.ieee.org
We have developed an integration technology for the single electron transistor (SET)/CMOS
hybrid systems. SET and CMOS transistors can be optimized without any possible …
hybrid systems. SET and CMOS transistors can be optimized without any possible …