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Block-based processor core composition register
Systems, apparatuses, and methods related to a block-based processor core composition
register are disclosed. In one example of the disclosed technology, a processor can include …
register are disclosed. In one example of the disclosed technology, a processor can include …
Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
Methods, procedures, apparatuses, computer programs, computer-accessible mediums,
processing arrangements and systems generally related to data multi-casting in a distrib …
processing arrangements and systems generally related to data multi-casting in a distrib …
Broadcast channel architectures for block-based processors
Apparatus and methods are disclosed for example computer processors that are based on a
hybrid dataflow execution model. In particular embodiments, a processor core in a block …
hybrid dataflow execution model. In particular embodiments, a processor core in a block …
Method, system and computer-accessible medium for providing a distributed predicate prediction
Examples of a system, method and computer accessible medium are provided to generate a
predicate prediction for a distributed multi-core architecture. Using Such system, method and …
predicate prediction for a distributed multi-core architecture. Using Such system, method and …
Combined branch target and predicate prediction
Embodiments provide methods, apparatus, systems, and computer readable media
associated with predicting predi cates and branch targets during execution of programs …
associated with predicting predi cates and branch targets during execution of programs …
Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
Systems, apparatuses, and methods related to a block-based processor core topology
register are disclosed. In one example of the disclosed technology, a processor can include …
register are disclosed. In one example of the disclosed technology, a processor can include …
Indirect branch target predictor that prevents speculation if mispredict is expected
AJ Beaumont-Smith, R Gunna - US Patent 8,555,040, 2013 - Google Patents
In one embodiment, a processor implements an indirect branch target predictor to predict
target addresses of indirect branch instructions. The indirect branch target predictor may …
target addresses of indirect branch instructions. The indirect branch target predictor may …
Initiating instruction block execution using a register access instruction
Apparatus and methods are disclosed for initiating instruc tion block execution using a
register access instruction (eg, a register Read instruction). In some examples of the dis …
register access instruction (eg, a register Read instruction). In some examples of the dis …
Debug support for block-based processor
Systems and methods are disclosed for supporting debug ging of programs in block-based
processor architectures. In one example of the disclosed technology, a processor includes a …
processor architectures. In one example of the disclosed technology, a processor includes a …
Write nullification
Apparatus and methods are disclosed for nullifying one or more registers identified in a
target field of a nullification instruction. In some examples of the disclosed technology, an …
target field of a nullification instruction. In some examples of the disclosed technology, an …