Error characterization, mitigation, and recovery in flash-memory-based solid-state drives
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …
continuously increased and cost has continuously decreased over decades. This positive …
Rowpress: Amplifying read disturbance in modern dram chips
Memory isolation is critical for system reliability, security, and safety. Unfortunately, read
disturbance can break memory isolation in modern DRAM chips. For example, RowHammer …
disturbance can break memory isolation in modern DRAM chips. For example, RowHammer …
Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly-accessed dram rows
Aggressive memory density scaling causes modern DRAM devices to suffer from
RowHammer, a phenomenon where rapidly activating (ie, hammering) a DRAM row can …
RowHammer, a phenomenon where rapidly activating (ie, hammering) a DRAM row can …
DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
A deeper look into rowhammer's sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (ie,
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
{MQSim}: A framework for enabling realistic studies of modern {Multi-Queue}{SSD} devices
Solid-state drives (SSDs) are used in a wide array of computer systems today, including in
datacenters and enterprise servers. As the I/O demands of these systems have increased …
datacenters and enterprise servers. As the I/O demands of these systems have increased …
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
D-RaNGe: Using commodity DRAM devices to generate true random numbers with low latency and high throughput
We propose a new DRAM-based true random number generator (TRNG) that leverages
DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access …
DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access …