Performance analysis of low-power 1-bit CMOS full adder cells
AM Shams, TK Darwish… - IEEE transactions on very …, 2002 - ieeexplore.ieee.org
A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized
into smaller modules. The modules are studied and evaluated extensively. Several designs …
into smaller modules. The modules are studied and evaluated extensively. Several designs …
Low-voltage low-power CMOS full adder
D Radhakrishnan - IEE Proceedings-Circuits, Devices and Systems, 2001 - IET
Low-power design of VLSI circuits has been identified as a critical technological need in
recent years due to the high demand for portable consumer electronics products. In this …
recent years due to the high demand for portable consumer electronics products. In this …
A 14-transistor CMOS full adder with full voltage-swing nodes
M Vesterbacka - 1999 IEEE Workshop on Signal Processing …, 1999 - ieeexplore.ieee.org
We explain how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general
full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also …
full adder circuit based on pass transistors. A six-transistor CMOS XOR circuit that also …
ULPFA: A new efficient design of a power-aware full adder
In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-
based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch …
based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch …
A 10-transistor low-power high-speed full adder cell
HA Mahmoud, MA Bayoumi - 1999 IEEE International …, 1999 - ieeexplore.ieee.org
In this paper, we introduce a high-speed low-power 10-transistor 1-bit full adder cell. The
critical path consists of an XOR gate; an inverter and one pass transistor. A prototype of the …
critical path consists of an XOR gate; an inverter and one pass transistor. A prototype of the …
Low power multipliers based on new hybrid full adders
Z Abid, H El-Razouk, DA El-Dib - Microelectronics Journal, 2008 - Elsevier
Five hybrid full adder designs are proposed for low power parallel multipliers. The new
adders allow NAND gates to generate most of the multiplier partial product bits instead of …
adders allow NAND gates to generate most of the multiplier partial product bits instead of …
Performance evaluation of 1-bit CMOS adder cells
A Shams, M Bayoumi - 1999 IEEE International Symposium on …, 1999 - ieeexplore.ieee.org
Evaluating the performance measures of a full adder cell, like other circuits, is input pattern
dependent. The issue gets more complicated when evaluating several parameters such as …
dependent. The issue gets more complicated when evaluating several parameters such as …
A structured approach for designing low power adders
AM Shams, MA Bayoumi - Conference Record of the Thirty-First …, 1997 - ieeexplore.ieee.org
A performance analysis of a general 1-bit full adder cell is presented. The adder cell is
anatomized into smaller modules using the proposed structured approach. The modules are …
anatomized into smaller modules using the proposed structured approach. The modules are …
Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops
JS Wang, PH Yang, D Sheng - IEEE Journal of Solid-State …, 2000 - ieeexplore.ieee.org
This paper describes the design of a low-power pipelined multiplier. It is illustrated in this
paper that the power consumption of the clocking system cannot be overlooked and the …
paper that the power consumption of the clocking system cannot be overlooked and the …
Nontraditional design of dynamic logics using FDSOI for ultra-efficient computing
In this article, we propose a nontraditional design of dynamic logic circuits using fully-
depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage () to be …
depleted silicon-on-insulator (FDSOI) FETs. FDSOI FET allows the threshold voltage () to be …